Using Multi-Layer/Multi-Input/Multi-Output (MLMIMO) Models for Metal-Gate Structures

• US 20100036518A1
• Filed: 08/06/2008
• Published: 02/11/2010
• Est. Priority Date: 08/06/2008
• Status: Active Grant

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: Sundararajan, Radha, Lee, Hyung Joo, Yamashita, Asao, Prager, Daniel, Funk, Merritt
• Granted Patent: US 7,894,927 B2
• Time in Patent Office: Days
• US Class Current: 700/121
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.

Claims

1. A method for using a Multi-Layer/Multi-Input/Multi-Output (MLMIMO) model comprising:

receiving a first set of patterned wafers and associated wafer data, each patterned wafer having a first patterned soft-mask layer and a plurality of additional layers, the first patterned soft-mask layer including a plurality of metal-gate-related soft-mask features and at least one first periodic evaluation structure, the wafer data including real-time integrated metrology (IM) data for the at least one first periodic evaluation structure in the first patterned soft-mask layer;

establishing a first Multi-Layer-Multi-Step (MLMS) processing sequence, wherein the first MLMS processing sequence comprises a first set of Poly-Etch procedures and is configured to establish a first gate-width control pattern in a first set of the additional layers using the first patterned soft-mask layer;

creating a second set of patterned wafers using the first MLMS processing sequence;

creating first simulation data for the first MLMS processing sequence using a first Multi-Layer/Multi-Input/Multi-Output (MLMIMO) model for the first MLMS processing sequence, wherein the first MLMIMO model includes a first number (N_a) of first Controlled Variables (CV_1a, CV_2a, . . . CV_Na), a first number (M_a) of first Manipulated Variables (MV_1a, MV_2a, . . . MV_Ma), and a first number (L_a) of first Disturbance Variables (DV_1a, DV_2a, . . . DV_La), wherein (L_a, M_a, and N_a) are integers greater than one;

establishing a second MLMS processing sequence, wherein the second MLMS processing sequence is configured to create a first controlled pattern of metal-gate structures by patterning a second set of the additional layers using the first gate-width control pattern;

creating a third set of patterned wafers using the second MLMS processing sequence;

creating second simulation data for the second MLMS processing sequence using a second MLMIMO model for the second MLMS processing sequence, wherein the second MLMIMO model includes a second number (N_b) of second Controlled Variables (CV_1b, CV_2b, . . . CV_Nb), a second number (M_b) of second Manipulated Variables (MV_1b, MV_2b, . . . MV_Mb), and a second number (L_b) of second Disturbance Variables (DV_1b, DV_2b, . . . DV_Lb), wherein (L_b, M_b, and N_b) are integers greater than one.

obtaining evaluation data for at least one of the third set of patterned wafers;

identifying the third set of patterned wafers as verified wafers when the evaluation data is less than a first metal-gate limit; and

performing a corrective action when the evaluation data is not less than the first metal-gate limit.

2. The method of claim 1, wherein a cleaning sequence is performed using the first set of patterned wafers, the second set of patterned wafers, or the third set of patterned wafers, or any combination thereof.

3. The method of claim 1, further comprising:

establishing the first number (L_a) of the first Disturbance Variables (DV_1a, DV_2a, . . . DV_La) using the real-time IM data associated with the first set of patterned wafers or additional measurement data;

establishing the first number (M_a) of first Manipulated Variables (MV_1a, MV_2a, . . . MV_Ma) using a first etching chamber, wherein the first set of (MV_1a, MV_2a, . . . MV_Ma) includes one or more Within-Wafer Manipulated Variables (WiW-MVs) configured to change while a wafer is being processed, and one or more Wafer-to-Wafer- Manipulated Variables (W2W-MVs) configured to change after the wafer has been processed; and

calculating the first number (N_a) of first Controlled Variables (CV_1a, CV_2a, . . . CV_Na), wherein

CV(N_a)=f_Na{MV_1a, . . . MV_Ma-1, MV_MA, DV_1a, . . . DV_La-1, DV_La}+OFFSET(N_a).

4. The method of claim 1, further comprising:

establishing the second number (L_b) of second Disturbance Variables (DV_1b, DV_2b, . . . DV_Lb) using the real-time IM data associated with the second set of patterned wafers;

establishing the second number (M_b) of second Manipulated Variables (MV_1b, MV_2b, . . . MV_Mb) using a second etching chamber, wherein the second set of second (MV_1b, MV_2b, . . . MV_Mb) includes one or more Within-Wafer Manipulated Variables (WiW-MVs) configured to change while a wafer is being processed, and one or more Wafer-to-Wafer- Manipulated Variables (W2W-MVs) configured to change after the wafer has been processed; and

calculating the second number (N_b) of second Controlled Variables (CV_1b, CV_2b, . . . CV_Nb), wherein

CV(N_b)=f_Nb{MV_1b, . . . MV_Mb-1, MV_Mb, DV_1b, . . . DV_Lb-1, DV_Lb}+OFFSET(N_b).

5. The method of claim 1, wherein the first Disturbance Variables (DV_1,1, DV_1,2, . . . DV_1,N1) comprises a first critical dimension (CD) of a first evaluation feature associated with a wafer edge, a second CD of a second evaluation feature associated with a wafer center, a first sidewall angle of the first evaluation feature associated with the wafer edge, a second sidewall angle of the second evaluation feature associated with the wafer center, a soft-mask layer thickness, a layer thickness for at least one of the additional layers an etch rate for the soft-mask layer, etch rates for one or more one of the additional layers, at least one etch chamber parameter, at least one integrated metrology (IM) device parameter, and at least one chamber maintenance parameter.

6. The method as claimed in claim 1, the first MLMS processing sequence further comprising:

transferring a first patterned to a first multi-zone temperature-controlled wafer holder in a first etching chamber using a transfer subsystem coupled to the first etching chamber, wherein the transfer subsystem is configured to prevent an oxide layer from forming on the first patterned during the transferring;

performing a first hard-mask layer etching procedure, wherein a first hard-mask layer comprises a Silicon-containing Anti-Reflective Coating (ARC) material and the first hard-mask layer etching procedure comprises;

establishing a first chamber pressure in the first etching chamber, wherein the first chamber pressure ranges from approximately 12 mT to approximately 18 mT;

establishing a first edge temperature and a first center temperature for the first multi-zone temperature-controlled wafer holder for a first time during the first hard-mask layer etching procedure, the first center temperature being between approximately 12 degrees Celsius and 20 degrees Celsius, the first edge temperature being between approximately 8 degrees Celsius and 12 degrees Celsius, and wherein a low temperature chiller is coupled to the first multi-zone temperature-controlled wafer holder, the low temperature chiller operating between approximately -20 degrees Celsius and 10 degrees Celsius during the first time;

establishing a first edge backside pressure and a first center backside pressure using a dual backside gas system in the first multi-zone temperature-controlled wafer holder, the first center backside pressure being between approximately 15 Torr and 25 Torr, the first edge backside pressure being between approximately 27 Torr and 33 Torr;

providing a first process gas into the first etching chamber during the first hard-mask layer etching procedure, wherein the first process gas includes CF₄ and CHF₃, a CF₄ flow rate varying between approximately 60 sccm and approximately 100 sccm and a first CHF₃ flow rate varying between approximately 40 sccm and approximately 60 sccm, wherein a gas injection system is configured to provide the first process gas to one or more areas of a processing region;

providing a first radio frequency (RF) power to a center region in the first etching chamber and providing a second RF power to an edge region in the first etching chamber using a first power splitter coupled to two upper electrodes in the first etching chamber, wherein a first RF source is coupled to the first power splitter, the first RF source operating in a first frequency range from approximately 0.1 MHz. to approximately 200 MHz, the first RF power ranging from approximately 450 watts to approximately 550 watts and the second RF power ranging from approximately 10 watts to approximately 100 watts during the first hard-mask layer etching procedure; and

providing a lower radio frequency (RF) power to a lower electrode in the first multi-zone temperature-controlled wafer holder using an RF generator and an impedance match network, the RF generator operating from approximately 0.1 MHz. to approximately 200 MHz, the first RF power ranging from approximately 450 watts to approximately 550 watts and the lower RF power ranging from approximately 90 watts to approximately 110 watts during the first hard-mask layer etching procedure.

7. The method as claimed in claim 6, further comprising:

creating a first simulation data subset for the first MLMS processing sequence using a first reduced MLMIMO model for the first hard-mask layer etching procedure, wherein the first reduced MLMIMO model includes a first reduced number (N_a1) of first Controlled Variables (CV_1a1, CV_2a1, . . . CV_Na1), a first reduced number (M_a1) of first Manipulated Variables (MV_1a1, MV_2a1, . . . MV_Ma1), and a first reduced number (L_a1) of the first Disturbance Variables (DV_1a1, DV_2a1, . . . DV_La1), wherein (L_a1, M_a1, and N_a1) are integers greater than one;

obtaining evaluation data for the first hard-mask layer etching procedure;

determining risk data for the first hard-mask layer etching procedure using differences between the first simulation data subset and the evaluation data for the first hard-mask layer etching procedure;

identifying the first hard-mask layer etching procedure as a verified procedure when first risk data is less than a first risk limit; and

identifying the first hard-mask layer etching procedure as a non-verified procedure when the first risk data is not less than the first risk limit.

8. The method as claimed in claim 1, the first MLMS processing sequence further comprising:

transferring a first patterned to a first multi-zone temperature-controlled wafer holder in a first etching chamber using a transfer subsystem coupled to the first etching chamber, wherein the transfer subsystem is configured to prevent an oxide layer from forming on the first patterned during the transferring;

performing a Si-ARC layer etching procedure;

performing a first etch-control layer (ECL) etching procedure, wherein the ECL comprises a gate-width control material and the ECL etching procedure comprises;

establishing a first chamber pressure in the first etching chamber, wherein the first chamber pressure ranges from approximately 15 mT to approximately 25 mT;

establishing a first edge temperature and a first center temperature for the first multi-zone temperature-controlled wafer holder during the ECL etching procedure, the first center temperature being between approximately 12 degrees Celsius and 20 degrees Celsius, the first edge temperature being between approximately 8 degrees Celsius and 12 degrees Celsius, and wherein a low temperature chiller is coupled to the first multi-zone temperature-controlled wafer holder, the low temperature chiller operating between approximately −

20 degrees Celsius and 10 degrees Celsius;

establishing a first edge backside pressure and a first center backside pressure using a dual backside gas system in the first multi-zone temperature-controlled wafer holder, the first center backside pressure being between approximately 15 Torr and 20 Torr, the first edge backside pressure being between approximately 27 Torr and 33 Torr;

providing a second process gas into the first etching chamber during the ECL etching procedure, wherein the second process gas includes O₂, CO₂,and HBr, a second O₂ flow rate varying between approximately 30 sccm and approximately 50 sccm, a second CO₂ flow rate varying between approximately 70 sccm and approximately 90 sccm and a second HBr flow rate varying between approximately 25 sccm and approximately 35 sccm, wherein a gas injection system is configured to provide the second process gas to one or more areas of a processing region;

providing a first radio frequency (RF) power to a center region in the first etching chamber and providing a second RF power to an edge region in the first etching chamber using a first power splitter coupled to two upper electrodes in the first etching chamber, wherein a first RF source is coupled to the first power splitter, the first RF source operating in a first frequency range from approximately 0.1 MHz. to approximately 200 MHz, the first RF power ranging from approximately 450 watts to approximately 550 watts and the second RF power ranging from approximately 10 watts to approximately 100 watts during the a first hard-mask layer etching procedure; and

providing a lower radio frequency (RF) power to a lower electrode in the first multi-zone temperature-controlled wafer holder using an RF generator and an impedance match network, the RF generator operating from approximately 0.1 MHz. to approximately 200 MHz, and the lower RF power ranging from approximately 90 watts to approximately 110 watts during the first hard-mask layer etching procedure.

9. The method as claimed in claim 8, further comprising:

creating a first simulation data subset for the first MLMS processing sequence using a first reduced MLMIMO model for the first ECL etching procedure, wherein the first reduced MLMIMO model includes a first reduced number (N_a1) of first Controlled Variables (CV_1a1, CV_2a1, . . . CV_Na1), a first reduced number (M_a1) of first Manipulated Variables (MV_1a1, MV_2a1, . . . MV_Ma1), and a first reduced number (L_a1) of the first Disturbance Variables (DV_1a1, DV_2a1, . . . DV_La1), wherein (L_a1, M_a1, and N_a1) are integers greater than one;

obtaining evaluation data for the first ECL etching procedure;

determining risk data for the first ECL etching procedure using differences between the first simulation data subset and the evaluation data for the first ECL etching procedure;

identifying the first ECL etching procedure as a verified procedure when first risk data is less than a first risk limit; and

identifying the first ECL etching procedure as a non-verified procedure when the first risk data is not less than the first risk limit.

10. The method as claimed in claim 1, the second MLMS processing sequence further comprising:

transferring a first patterned to a first multi-zone temperature-controlled wafer holder in a first etching chamber using a transfer subsystem coupled to the first etching chamber, wherein the transfer subsystem is configured to prevent an oxide layer from forming on the first patterned during the transferring;

performing a Si-ARC layer etching procedure, and/or an Etch-Control Layer (ECL) etching procedure;

performing a second hard-mask layer etching procedure, wherein a second hard-mask layer comprises Tetraethyl Orthosilicate (TEOS) material and the second hard-mask layer etching procedure comprises;

establishing a first chamber pressure in the first etching chamber during the second hard-mask layer etching procedure, wherein the first chamber pressure ranges from approximately 35 mT to approximately 45 mT;

establishing a first edge temperature and a first center temperature for the first multi-zone temperature-controlled wafer holder for a first time during a first hard-mask layer etching procedure, the first center temperature being between approximately 25 degrees Celsius and approximately 35 degrees Celsius, the first edge temperature being between approximately 8 degrees Celsius and approximately 12 degrees Celsius, and wherein a low temperature chiller is coupled to the first multi-zone temperature-controlled wafer holder, the low temperature chiller operating between approximately −

20 degrees Celsius and 10 degrees Celsius during the first time;

establishing a first edge backside pressure and a first center backside pressure using a dual backside gas system in the first multi-zone temperature-controlled wafer holder, the first center backside pressure being between approximately 15 Torr and 25 Torr, the first edge backside pressure being between approximately 27 Torr and 33 Torr. providing a first process gas into the first etching chamber during the second hard-mask layer etching procedure, wherein the first process gas includes CF₄, CHF₃, and O₂, a first CF₄ flow rate varying between approximately 40 sccm and approximately 60 sccm, a first CHF₃ flow rate varying between approximately 40 sccm and approximately 60 sccm and a first O₂ flow rate varying between approximately 3 sccm and approximately 7 sccm, wherein a gas injection system is configured to provide the first process gas to one or more areas of a processing region;

providing a first radio frequency (RF) power to a center region in the first etching chamber and providing a second RF power to an edge region in the first etching chamber using a first power splitter coupled to two upper electrodes in the first etching chamber, wherein a first RF source is coupled to the first power splitter, the first RF source operating in a first frequency range from approximately 0.1 MHz. to approximately 200 MHz, the first RF power ranging from approximately 550 watts to approximately 650 watts and the second RF power ranging from approximately 50 watts to approximately 150 watts during the second hard-mask layer etching procedure; and

providing a lower radio frequency (RF) power to a lower electrode in the first multi-zone temperature-controlled wafer holder using an RF generator and an impedance match network, the RF generator operating from approximately 0.1 MHz. to approximately 200 MHz, and the lower RF power ranging from approximately 90 watts to approximately 110 watts during the second hard-mask layer etching procedure.

11. The method as claimed in claim 10, further comprising:

creating a first simulation data subset for the first MLMS processing sequence using a first reduced MLMIMO model for the second hard-mask layer etching procedure, wherein the first reduced MLMIMO model includes a first reduced number (N_a1) of first Controlled Variables (CV_1a1, CV_2a1, . . . CV_Na1), a first reduced number (M_a1) of first Manipulated Variables (MV_1a1, MV_2a1, . . . MV_Ma1), and a first reduced number (L_a1) of the first Disturbance Variables (DV_1a1, DV_2a1, . . . DV_La1), wherein (L_a1, M_a1, and N_a1) are integers greater than one;

obtaining evaluation data for the second hard-mask layer etching procedure;

determining risk data for the second hard-mask layer etching procedure using differences between the first simulation data subset and the evaluation data for the second hard-mask layer etching procedure;

identifying the second hard-mask layer etching procedure as a verified procedure when first risk data is less than a first risk limit; and

identifying the second hard-mask layer etching procedure as a non-verified procedure when the first risk data is not less than the first risk limit.

12. The method as claimed in claim 1, further comprising:

transferring a first patterned to a first multi-zone temperature-controlled wafer holder in a first etching chamber using a transfer subsystem coupled to the first etching chamber, wherein the transfer subsystem is configured to prevent an oxide layer from forming on the first patterned during the transferring;

performing a Si-ARC layer etching procedure, or an Etch-Control Layer (ECL) etching procedure, or a second hard-mask layer etching procedure, or any combination thereof;

performing a TEOS Over-Etch (OE) etching procedure, wherein the TEOS OE etching procedure comprises;

establishing a first chamber pressure in the first etching chamber during the TEOS OE etching procedure, wherein the first chamber pressure ranges from approximately 35 mT to approximately 45 mT;

establishing a first edge temperature and a first center temperature for the first multi-zone temperature-controlled wafer holder for a first time during the during the TEOS OE etching procedure, the first center temperature being between approximately 25 degrees Celsius and approximately 35 degrees Celsius, the first edge temperature being between approximately 8 degrees Celsius and approximately 12 degrees Celsius, and wherein a low temperature chiller is coupled to the first multi-zone temperature-controlled wafer holder, the low temperature chiller operating between approximately −

20 degrees Celsius and 10 degrees Celsius during the first time;

establishing a first edge backside pressure and a first center backside pressure using a dual backside gas system in the first multi-zone temperature-controlled wafer holder, the first center backside pressure being between approximately 15 Torr and 25 Torr, the first edge backside pressure being between approximately 27 Torr and 33 Torr;

providing a first process gas into the first etching chamber during the TEOS OE etching procedure, wherein the first process gas includes CF₄, CHF₃, and O₂, a first CF₄ flow rate varying between approximately 40 sccm and approximately 60 sccm, a first CHF₃ flow rate varying between approximately 40 sccm and approximately 60 sccm and a first O₂ flow rate varying between approximately 3 sccm and approximately 7 sccm, wherein a gas injection system is configured to provide the first process gas to one or more areas of a processing region;

providing a first radio frequency (RF) power to a center region in the first etching chamber and providing a second RF power to an edge region in the first etching chamber using a first power splitter coupled to two upper electrodes in the first etching chamber, wherein a first RF source is coupled to the first power splitter, the first RF source operating in a first frequency range from approximately 0.1 MHz. to approximately 200 MHz, the first RF power ranging from approximately 550 watts to approximately 650 watts and the second RF power ranging from approximately 50 watts to approximately 150 watts during the TEOS OE etching procedure; and

providing a lower radio frequency (RF) power to a lower electrode in the first multi-zone temperature-controlled wafer holder using an RF generator and an impedance match network, the RF generator operating from approximately 0.1 MHz. to approximately 200 MHz, and the lower RF power ranging from approximately 90 watts to approximately 110 watts during the TEOS OE etching procedure.

13. The method as claimed in claim 12, further comprising:

creating a first simulation data subset for the first MLMS processing sequence using a first reduced MLMIMO model for the TEOS OE etching procedure, wherein the first reduced MLMIMO model includes a first reduced number (N_a1) of first Controlled Variables (CV_1a1, CV_2a1, . . . CV_Na1), a first reduced number (M_a1) of first Manipulated Variables (MV_1a1, MV_2a1, . . . MV_Ma1), and a first reduced number (L_a1) of the first Disturbance Variables (DV_1a1, DV_2a1, . . . DV_La1), wherein (L_a1, M_a1, and N_a1) are integers greater than one;

obtaining evaluation data for the TEOS OE etching procedure;

determining risk data for the TEOS OE etching procedure using differences between the first simulation data subset and the evaluation data for the TEOS OE etching procedure;

identifying the TEOS OE etching procedure as a verified procedure when first risk data is less than a first risk limit; and

identifying the TEOS OE etching procedure as a non-verified procedure when the first risk data is not less than the first risk limit;

14. The method as claimed in claim 1, further comprising:

transferring a first patterned to a first multi-zone temperature-controlled wafer holder in a first etching chamber using a transfer subsystem coupled to the first etching chamber, wherein the transfer subsystem is configured to prevent an oxide layer from forming on the first patterned during the transferring;

performing a Si-ARC layer etching procedure, or an Etch-Control Layer (ECL) etching procedure, or a second hard-mask layer etching procedure or an Over-Etch (OE) etching procedure, or any combination thereof;

transferring the first patterned to the first multi-zone temperature-controlled wafer holder in a first ashing chamber using the transfer subsystem coupled to the first ashing chamber;

performing an ashing procedure, wherein the ashing procedure comprises;

establishing a first chamber pressure in the first ashing chamber during the ashing procedure, wherein the first chamber pressure ranges from approximately 125 mT to approximately 175 mT;

establishing a first edge temperature and a first center temperature for the first multi-zone temperature-controlled wafer holder during the during the ashing procedure, the first center temperature being between approximately 70 degrees Celsius and approximately 80 degrees Celsius, the first edge temperature being between approximately 8 degrees Celsius and approximately 12 degrees Celsius, and wherein a low temperature chiller is coupled to the first multi-zone temperature-controlled wafer holder, the low temperature chiller operating between approximately −

20 degrees Celsius and 10 degrees Celsius during the ashing procedure;

establishing a first edge backside pressure and a first center backside pressure using a dual backside gas system in the first multi-zone temperature-controlled wafer holder, the first center backside pressure being between approximately 15 Torr and 25 Torr, the first edge backside pressure being between approximately 27 Torr and 33 Torr;

providing a first process gas into the first ashing chamber during the ashing procedure, wherein the first process gas includes O₂, a first O₂ flow rate varying between approximately 430 sccm and approximately 470 sccm, wherein a gas injection system is configured to provide the first process gas to one or more areas of a processing region;

providing a first radio frequency (RF) power to a center region in the first ashing chamber and providing a second RF power to an edge region in the first ashing chamber using a first power splitter coupled to two upper electrodes in the first ashing chamber, wherein a first RF source is coupled to the first power splitter, the first RF source operating in a first frequency range from approximately 0.1 MHz. to approximately 200 MHz, the first RF power ranging from approximately 350 watts to approximately 450 watts and the second RF power ranging from approximately 10 watts to approximately 100 watts during the ashing procedure; and

providing a lower radio frequency (RF) power to a lower electrode in the first multi-zone temperature-controlled wafer holder using an RF generator and an impedance match network, the RF generator operating from approximately 0.1 MHz. to approximately 200 MHz, and the lower RF power ranging from approximately 20 watts to approximately 30 watts during the ashing procedure.

15. The method as claimed in claim 14, further comprising:

creating a first simulation data subset for the first MLMS processing sequence using a first reduced MLMIMO model for the ashing procedure, wherein the first reduced MLMIMO model includes a first reduced number (N_a1) of first Controlled Variables (CV_1a1, CV_2a1, . . . CV_Na1), a first reduced number (M_a1) of first Manipulated Variables (MV_1a1, MV_2a1, . . . MV_Ma1), and a first reduced number (L_a1of the first Disturbance Variables (DV_1a1, DV_2a1, . . . DV_La1), wherein (L_a1, M_a1, and N_a1) are greater than one;

obtaining evaluation data for the ashing procedure;

determining risk data for the ashing procedure using differences between the first simulation data subset and the evaluation data for the ashing procedure;

identifying the ashing procedure as a verified procedure when first risk data is less than a first risk limit; and

identifying the ashing procedure as a non-verified procedure when the first risk data is not less than the first risk limit.

16. The method as claimed in claim 1, further comprising:

performing a first Multi-Layer-Multi-Step MLMS processing sequence, wherein the second set of patterned wafers is created;

transferring a first one of the second set of patterned wafers to a first multi-zone temperature-controlled wafer holder in a first etching chamber using a transfer subsystem coupled to the first etching chamber, wherein the transfer subsystem is configured to prevent an oxide layer from forming on the first patterned during the transferring;

performing a Break-Through (BT) etching procedure, wherein the BT etching procedure comprises;

establishing a first chamber pressure in the first etching chamber during the BT etching procedure, wherein the first chamber pressure ranges from approximately 8 mT to approximately 12 mT;

establishing a first edge temperature and a first center temperature for the first multi-zone temperature-controlled wafer holder during the during the BT etching procedure, the first center temperature being between approximately 70 degrees Celsius and approximately 80 degrees Celsius, the first edge temperature being between approximately 8 degrees Celsius and approximately 12 degrees Celsius, and wherein a low temperature chiller is coupled to the first multi-zone temperature-controlled wafer holder, the low temperature chiller operating between approximately −

20 degrees Celsius and 10 degrees Celsius during the BT etching procedure;

establishing a first edge backside pressure and a first center backside pressure using a dual backside gas system in the first multi-zone temperature-controlled wafer holder, the first center backside pressure being between approximately 8 Torr and 12 Torr, the first edge backside pressure being between approximately 8 Torr and 12 Torr;

providing a first process gas into the first etching chamber during the BT etching procedure, wherein the first process gas includes CF₄, a first CF₄ flow rate varying between approximately 120 sccm and approximately 150 sccm, wherein a gas injection system is configured to provide the first process gas to one or more areas of a processing region;

providing a first radio frequency (RF) power to a center region in the first etching chamber and providing a second RF power to an edge region in the first etching chamber using a first power splitter coupled to two upper electrodes in the first etching chamber, wherein a first RF source is coupled to the first power splitter, the first RF source operating in a first frequency range from approximately 0.1 MHz. to approximately 200 MHz, the first RF power ranging from approximately 600 watts to approximately 700 watts and the second RF power ranging from approximately 10 watts to approximately 100 watts during the BT etching procedure; and

providing a lower radio frequency (RF) power to a lower electrode in the first multi-zone temperature-controlled wafer holder using an RF generator and an impedance match network, the RF generator operating from approximately 0.1 MHz. to approximately 200 MHz, and the lower RF power ranging from approximately 175 watts to approximately 200 watts during the BT etching procedure.

17. The method as claimed in claim 16, further comprising:

creating a second simulation data subset for the second MLMS processing sequence using a second reduced MLMIMO model for the BT etching procedure, wherein the second reduced MLMIMO model includes a second reduced number (N_b1) of first Controlled Variables (CV_1b1, CV_2b1, . . . CV_Nb1), a second reduced number (M_b1) of second Manipulated Variables (MV_1b1, MV_2b1, . . . MV_Mb1), and a second reduced number (L_b1) of second Disturbance Variables (DV_1b1, DV_2b1, . . . DV_Lb1), wherein (L_b1, M_b1, and N_b1) are integers greater than one;

obtaining second evaluation data for the BT etching procedure;

determining second risk data for the BT etching procedure using differences between the second simulation data subset and the second evaluation data for the BT etching procedure;

identifying the BT etching procedure as a verified procedure when second risk data is less than a second risk limit; and

identifying the BT etching procedure as a non-verified procedure when the second risk data is not less than the second risk limit.

18. The method as claimed in claim 1, further comprising:

performing a first Multi-Layer-Multi-Step MLMS processing sequence, wherein the second set of patterned wafers is created;

transferring a first one of the second set of patterned wafers to a first multi-zone temperature-controlled wafer holder in a first etching chamber using a transfer subsystem coupled to the first etching chamber, wherein the transfer subsystem is configured to prevent an oxide layer from forming on the first patterned during the transferring;

performing a Break-Through (BT) etching procedure;

performing a Main-Etch (ME) etching procedure, wherein the ME etching procedure comprises;

establishing a first chamber pressure in the first etching chamber during the ME etching procedure, wherein the first chamber pressure ranges from approximately 8 mT to approximately 12 mT;

establishing a first edge temperature and a first center temperature for the first multi-zone temperature-controlled wafer holder during the during the ME etching procedure, the first center temperature being between approximately 70 degrees Celsius and approximately 80 degrees Celsius, the first edge temperature being between approximately 8 degrees Celsius and approximately 12 degrees Celsius, and wherein a low temperature chiller is coupled to the first multi-zone temperature-controlled wafer holder, the low temperature chiller operating between approximately −

20 degrees Celsius and 10 degrees Celsius during the ME etching procedure;

establishing a first edge backside pressure and a first center backside pressure using a dual backside gas system in the first multi-zone temperature-controlled wafer holder, the first center backside pressure being between approximately 8 Torr and 12 Torr, the first edge backside pressure being between approximately 8 Torr and 12 Torr;

providing a first process gas into the first etching chamber during the ME etching procedure, wherein the first process gas includes CF₄, a first CF₄ flow rate varying between approximately 120 sccm and approximately 150 sccm, wherein a gas injection system is configured to provide the first process gas to one or more areas of a processing region;

providing a first radio frequency (RF) power to a center region in the first etching chamber and providing a second RF power to an edge region in the first etching chamber using a first power splitter coupled to two upper electrodes in the first etching chamber, wherein a first RF source is coupled to the first power splitter, the first RF source operating in a first frequency range from approximately 0.1 MHz. to approximately 200 MHz, the first RF power ranging from approximately 120 watts to approximately 150 watts and the second RF power ranging from approximately 0 watts to approximately 100 watts during the ME etching procedure; and

providing a lower radio frequency (RF) power to a lower electrode in the first multi-zone temperature-controlled wafer holder using an RF generator and an impedance match network, the RF generator operating from approximately 0.1 MHz. to approximately 200 MHz, and the lower RF power ranging from approximately 0 watts to approximately 10 watts during the ME etching procedure.

19. The method as claimed in claim 18, further comprising:

creating a second simulation data subset for the second MLMS processing sequence using a second reduced MLMIMO model for the ME etching procedure, wherein the second reduced MLMIMO model includes a second reduced number (N_b1) of first Controlled Variables (CV_1b1, CV_2b1, . . . CVN_Nb1), a second reduced number (M_b1) of second Manipulated Variables (MV_1b1, MV_2b1, . . . MV_Mb1), and a second reduced number (L_b1) of second Disturbance Variables (DV_1b1, DV_2b1, . . . DV_Lb1), wherein (L_b1, M_b1, and N_b1) are integers greater than one;

obtaining second evaluation data for the ME etching procedure;

determining second risk data for the ME etching procedure using differences between the second simulation data subset and the second evaluation data for the ME etching procedure;

identifying the ME etching procedure as a verified procedure when second risk data is less than a second risk limit; and

identifying the ME etching procedure as a non-verified procedure when the second risk data is not less than the second risk limit.

20. The method as claimed in claim 1, further comprising:

performing a first Multi-Layer-Multi-Step MLMS processing sequence, wherein the second set of patterned wafers is created;

transferring a first one of the second set of patterned wafers to a first multi-zone temperature-controlled wafer holder in a first etching chamber using a transfer subsystem coupled to the first etching chamber, wherein the transfer subsystem is configured to prevent an oxide layer from forming on the first patterned during the transferring;

performing a Break-Through (BT) etching procedure and/or a Main-Etch (ME) etching procedure;

performing an Over-Etch (OE) etching procedure, wherein the OE etching procedure comprises;

establishing a first chamber pressure in the first etching chamber during the OE etching procedure, wherein the first chamber pressure ranges from approximately 8 mT to approximately 12 mT;

establishing a first edge temperature and a first center temperature for the first multi-zone temperature-controlled wafer holder during the during the OE etching procedure, the first center temperature being between approximately 70 degrees Celsius and approximately 80 degrees Celsius, the first edge temperature being between approximately 8 degrees Celsius and approximately 12 degrees Celsius, and wherein a low temperature chiller is coupled to the first multi-zone temperature-controlled wafer holder, the low temperature chiller operating between approximately -20 degrees Celsius and 10 degrees Celsius during the OE etching procedure;

establishing a first edge backside pressure and a first center backside pressure using a dual backside gas system in the first multi-zone temperature-controlled wafer holder, the first center backside pressure being between approximately 8 Torr and 12 Torr, the first edge backside pressure being between approximately 8 Torr and 12 Torr;

providing a first process gas into the first etching chamber during the OE etching procedure, wherein the first process gas includes O₂ and HBr, a first O₂ flow rate varying between approximately 2 sccm and approximately 6 sccm, a first HBr flow rate varying between approximately 220 sccm and approximately 280 sccm, wherein a gas injection system is configured to provide the first process gas to one or more areas of a processing region;

providing a first radio frequency (RF) power to a center region in the first etching chamber and providing a second RF power to an edge region in the first etching chamber using a first power splitter coupled to two upper electrodes in the first etching chamber, wherein a first RF source is coupled to the first power splitter, the first RF source operating in a first frequency range from approximately 0.1 MHz. to approximately 200 MHz, the first RF power ranging from approximately 120 watts to approximately 150 watts and the second RF power ranging from approximately 0 watts to approximately 100 watts during the ME etching procedure; and

providing a lower radio frequency (RF) power to a lower electrode in the first multi-zone temperature-controlled wafer holder using an RF generator and an impedance match network, the RF generator operating from approximately 0.1 MHz. to approximately 200 MHz, and the lower RF power ranging from approximately 20 watts to approximately 40 watts during the OE etching procedure.

21. The method as claimed in claim 20, further comprising:

creating a second simulation data subset for the second MLMS processing sequence using a second reduced MLMIMO model for the OE etching procedure, wherein the second reduced MLMIMO model includes a second reduced number (N_b1) of first Controlled Variables (CV_1b1, CV_2b1, . . . CV_Nb1), a second reduced number (M_b1) of second Manipulated Variables (MV_1b1, MV_2b1, . . . MV_Mb1), and a second reduced number (L_b1) of second Disturbance Variables (DV_1b1, DV_2b1, . . . DV_Lb1), wherein (L_b1, M_b1, and N_b1) are integers greater than one;

obtaining second evaluation data for the OE etching procedure;

determining second risk data for the OE etching procedure using differences between the second simulation data subset and the second evaluation data for the OE etching procedure;

identifying the OE etching procedure as a verified procedure when second risk data is less than a second risk limit; and

identifying the OE etching procedure as a non-verified procedure when the second risk data is not less than the second risk limit.

22. The method as claimed in claim 1, further comprising:

performing a first Multi-Layer-Multi-Step MLMS processing sequence, wherein the second set of patterned wafers is created;

transferring a first one of the second set of patterned wafers to a first multi-zone temperature-controlled wafer holder in a first etching chamber using a transfer subsystem coupled to the first etching chamber, wherein the transfer subsystem is configured to prevent an oxide layer from forming on the first patterned during the transferring;

performing a Break-Through (BT) etching procedure, or a Main-Etch (ME) etching procedure, or an OE etching procedure, or any combination thereof;

performing a Titanium-Nitride (TiN) etching procedure, wherein the TiN etching procedure comprises;

establishing a first chamber pressure in the first etching chamber during the TiN etching procedure, wherein the first chamber pressure ranges from approximately 8 mT to approximately 12 mT;

establishing a first edge temperature and a first center temperature for the first multi-zone temperature-controlled wafer holder during the during the TiN etching procedure, the first center temperature being between approximately 70 degrees Celsius and approximately 80 degrees Celsius, the first edge temperature being between approximately 8 degrees Celsius and approximately 12 degrees Celsius, and wherein a low temperature chiller is coupled to the first multi-zone temperature-controlled wafer holder, the low temperature chiller operating between approximately −

20 degrees Celsius and 10 degrees Celsius during the TiN etching procedure;

establishing a first edge backside pressure and a first center backside pressure using a dual backside gas system in the first multi-zone temperature-controlled wafer holder, the first center backside pressure being between approximately 8 Torr and 12 Torr, the first edge backside pressure being between approximately 8 Torr and 12 Torr;

providing a first process gas into the first etching chamber during the TiN etching procedure, wherein the first process gas includes C1₂, a first C1₂ flow rate varying between approximately 12 sccm and approximately 18 sccm, wherein a gas injection system is configured to provide the first process gas to one or more areas of a processing region;

providing a first radio frequency (RF) power to a center region in the first etching chamber and providing a second RF power to an edge region in the first etching chamber using a first power splitter coupled to two upper electrodes in the first etching chamber, wherein a first RF source is coupled to the first power splitter, the first RF source operating in a first frequency range from approximately 0.1 MHz. to approximately 200 MHz, the first RF power ranging from approximately 180 watts to approximately 220 watts and the second RF power ranging from approximately 0 watts to approximately 100 watts during the ME etching procedure; and

providing a lower radio frequency (RF) power to a lower electrode in the first multi-zone temperature-controlled wafer holder using an RF generator and an impedance match network, the RF generator operating from approximately 0.1 MHz. to approximately 200 MHz, and the lower RF power ranging from approximately 40 watts to approximately 60 watts during the TiN etching procedure.

23. The method as claimed in claim 22, further comprising:

creating a second simulation data subset for the second MLMS processing sequence using a second reduced MLMIMO model for the TiN etching procedure, wherein the second reduced MLMIMO model includes a second reduced number (N_b1) of first Controlled Variables (CV_1b1, CV_2b1, . . . CV_Nb1), a second reduced number (M_b1) of second Manipulated Variables (MV_1b1, MV_2b1, . . . MV_Mb1), and a second reduced number (L_b1) of second Disturbance Variables (DV_1b1, DV_2b1, . . . DV_Lb1), wherein (L_b1, M_b1, and N_b1) are integers greater than one;

obtaining second evaluation data for the TiN etching procedure;

determining second risk data for the TiN etching procedure using differences between the second simulation data subset and the second evaluation data for the TiN etching procedure;

identifying the TiN etching procedure as a verified procedure when second risk data is less than a second risk limit; and

identifying the TiN etching procedure as a non-verified procedure when the second risk data is not less than the second risk limit.

24. The method as claimed in claim 1, further comprising:

performing a first Multi-Layer-Multi-Step MLMS processing sequence, wherein the second set of patterned wafers is created;

performing a Break-Through (BT) etching procedure, or a Main-Etch (ME) etching procedure, or an OE etching procedure, or a Titanium-Nitride (TiN) etching procedure, or any combination thereof;

transferring at least one of the second set of patterned wafers to a first multi-zone temperature-controlled wafer holder in a first etching chamber using a transfer subsystem coupled to the first etching chamber, wherein the transfer subsystem is configured to prevent an oxide layer from forming on the first patterned during the transferring;

performing a High-K (HK) etching procedure, wherein the HK etching procedure comprises;

establishing a first chamber pressure in the first etching chamber during the HK etching procedure, wherein the first chamber pressure ranges from approximately 8 mT to approximately 12 mT;

establishing a first temperature for the first multi-zone temperature-controlled wafer holder during the during the HK etching procedure, the first temperature being between approximately 350 degrees Celsius and approximately 390 degrees Celsius;

providing a first process gas into the first etching chamber during the HK etching procedure, wherein the first process gas includes BCl₃, a first BCl₃ flow rate varying between approximately 130 sccm and approximately 180 sccm, wherein a gas injection system is configured to provide the first process gas to one or more areas of a processing region; and

providing a first radio frequency (RF) power to a center region in the first etching chamber and providing a second RF power to an edge region in the first etching chamber using a first power splitter coupled to two upper electrodes in the first etching chamber, wherein a first RF source is coupled to the first power splitter, the first RF source operating in a first frequency range from approximately 0.1 MHz. to approximately 200 MHz, the first RF power ranging from approximately 550 watts to approximately 650 watts and the second RF power ranging from approximately 0 watts to approximately 100 watts during the HK etching procedure.

25. The method as claimed in claim 24, further comprising:

creating a second simulation data subset for the second MLMS processing sequence using a second reduced MLMIMO model for the HK etching procedure, wherein the second reduced MLMIMO model includes a second reduced number (N_b1) of first Controlled Variables (CV_1b1, CV_2b1, . . . CV_Nb1), a second reduced number (M_b1) of second Manipulated Variables (MV_1b1, MV_2b1, . . . MV_Mb1), and a second reduced number (L_b1) of second Disturbance Variables (DV_1b1, DV_2b1, . . . DV_Lb1), wherein (L_b1, M_b1, and N_b1) are integers greater than one;

obtaining second evaluation data for the HK etching procedure;

determining second risk data for the HK etching procedure using differences between the second simulation data subset and the second evaluation data for the HK etching procedure;

identifying the HK etching procedure as a verified procedure when second risk data is less than a second risk limit; and

identifying the HK etching procedure as a non-verified procedure when the second risk data is not less than the second risk limit.

26. The method as claimed in claim 1, wherein the metal-gate structures, include pFET structures, nFET structures, Tri-gate structures, and FinFET structures;

27. A method for using a Multi-Layer/Multi-Input/Multi-Output (MLMIMO) model to create metal-gate structures on a plurality of wafers, the method comprising:

a) receiving a first set of send-ahead wafers and associated wafer data, the wafer data including real-time and historical data;

b) establishing a first number (la) of disturbance variables DV(La) for a first multi-layer etch sequence and a second number (lb) of disturbance variables DV(Lb) for a second multi-layer etch sequence using real-time integrated metrology (IM) data associated with a patterned photoresist layer on one or more of the send-ahead wafers, wherein the real-time IM data includes critical dimension (CD) data, sidewall angle (SWA) data, thickness data, photoresist data, BARC data, the wafer data, and diffraction signal data from multiple sites in the patterned photoresist layer on each incoming wafer, wherein (La) and (Lb) are integers greater than two;

c) establishing a first number (Ma) of manipulated variables MV(Ma) for the first multi-layer etch sequence and a second number (Mb) of manipulated variables MV(Mb) for a second multi-layer etch sequence, wherein (Ma) and (Mb) are integers greater than two;

d) establishing a first number (Na) of controlled variables for the first multi-layer etch sequence and a second number (Nb) of controlled variables for the second multi-layer etch sequence, wherein (Na) and (Nb) are integer greater than two, wherein CV(Na) is defined as

CV(Na)=f_Na{MV(1a) . . . MV(Ma-1), MV(Ma), DV(1), . . . DV(La-1), DV(La)}+OFFSETS_Na

and CV(Nb) is defined as

CV(Nb)=f_Nb{MV(1b) . . . MV(Mb-1), MV(Mb), DV(1), . . . DV(Lb-1), DV(Lb)}+OFFSETS_Nb

e) calculating optimized process settings using a first quadratic objective function, wherein first target deviations t(Na) for the first multi-layer etch sequence are defined as;

t(Na)={DV(Na}−

target CV(Na)};

f) calculating optimized process settings using a second quadratic objective function, wherein second target deviations t(Nb) for the second multi-layer etch sequence are defined as;

t(Nb)={DV(Nb}−

target CV(Nb)};

g) defining adjusted process recipes for the first multi-layer etch sequence and/or the second multi-layer etch sequence using one or more calculated manipulated variables established during nonlinear programming;

h) processing one or more of the first set of send-ahead wafers using the adjusted process recipes;

i) obtaining additional measurement data for one or more of the send-ahead wafers, wherein new controlled variable data are obtained and filtered;

j) calculating one or more process errors using differences between the new controlled variable data and predicted controlled variable data;

k) calculating feedback data items, wherein errors are used to update the OFFSETS_Na for the first multi-layer etch sequence and/or the OFFSETS_Nb for the second multi-layer etch sequence using an exponentially weighted moving average (EWMA) filter;

l) updating the OFFSETS_Na for the first multi-layer etch sequence and/or the OFFSETS_Nb for the second multi-layer etch sequence in an optimizer unit; and

m) repeating steps a)-l) using each wafer in the first set of send-ahead wafers.

28. The method as claimed in claim 27, wherein first manipulated variables are calculated for the first multi-layer etch sequence by performing nonlinear programming using the first quadratic objective function defined as,

29. The method as claimed in claim 28, wherein second manipulated variables are calculated for the second multi-layer etch sequence by performing nonlinear programming using the second quadratic objective function defined as,

30. The method as claimed in claim 29, wherein the weighting factors w_ja, w_jb are dynamically updated based on one or more feedback errors.

31. The method as claimed in claim 29, wherein one or more controlled variable targets are prioritized when one or more manipulated variables are outside an allowable process window.

32. The method as claimed in claim 29, wherein the adjusted process recipes are defined using process state data and/or chamber state data.