SEMICONDUCTOR STORAGE DEVICE, METHOD OF CONTROLLING THE SAME, CONTROLLER AND INFORMATION PROCESSING APPARATUS

• US 20100037009A1
• Filed: 09/02/2009
• Published: 02/11/2010
• Est. Priority Date: 12/28/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Asano, Shigehiro, Matsuzaki, Hidenori, Kanno, Shinichi, Kitsunai, Kazuya, Hida, Toshikatsu, Yano, Hirokuni
• Granted Patent: US 8,065,470 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits

Abstract

A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Claims

1. A semiconductor storage device comprising:

a first memory area configured in a volatile semiconductor memory which performs writing of data by a first unit or less, the first unit being an access unit to the semiconductor storage device;

second and third memory areas configured in a nonvolatile semiconductor memory which performs writing of data by a second unit and performs erasing of data by a third unit, the third unit being twice or larger natural number times as large as the second unit; and

a controller executing;

a first processing for storing a plurality of data by the first unit in the first memory area;

a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, the first management unit being twice or larger natural number times as large as the first unit and being less than the third unit; and

a third processing for storing data outputted from the first memory area by a second management unit in the third memory area, the second management unit being twice or larger natural number times as large as the first management unit.

2. The semiconductor storage device according to claim 1, wherein in the second processing, the controller:

reads data which composes data of the first management unit and is not stored in the first memory area from at least one of the second and third memory areas; and

merges data stored in the first memory area and data read from at least one of the second and third memory areas into data of the first management unit.

3. The semiconductor storage device according to claim 1, wherein in the third processing, the controller:

reads data which composes data of the second management unit and is not stored in the first memory area from at least one of the second and third memory areas; and

merges data stored in the first memory area and data read from at least one of the second and third memory areas into data of the second management unit.

4. The semiconductor storage device according to claim 1, wherein the controller executes:

a fourth processing for selecting data of the first management unit to be outputted from the second memory area; and

a fifth processing for storing data including the selected data by the second management unit in the third memory area.

5. The semiconductor storage device according to claim 4, wherein in the fifth processing, the controller:

calculates logical address range by aligning logical address of the selected data into the second management unit;

reads data included in the logical address range from at least one of the first, second, and third memory areas; and

merges the selected data and data read from at least one of the first, second, and third memory areas into data of the second management unit.

6. The semiconductor storage device according to claim 1, wherein

the second and third memory areas share the same nonvolatile semiconductor memory, and

the controller allocates areas of the third unit to the second and third memory areas respectively.

7. The semiconductor storage device according to claim 1, wherein in the first processing, the controller:

calculates logical address range by aligning logical address of data inputted to the semiconductor storage device into the first management unit; and

stores data of the first unit in an area of the first management unit corresponding to the logical address range in the first memory area.

8. The semiconductor storage device according to claim 7, wherein in the first processing, the controller:

judges whether the logical address range is available for storing data of the first unit in the first memory area; and

executes at least one of the second and third processing if the logical address range is not available.

9. The semiconductor storage device according to claim 1, wherein the controller:

calculates logical address range by aligning logical address of data to be outputted from the first memory area into the second management unit;

counts data of the first management unit which is included in the logical address range and is stored in the first memory area;

executes the second processing if the sum of counted data is less than a predetermined threshold value; and

executes the third processing if the sum of counted data is equal to the predetermined threshold value or more.

10. The semiconductor storage device according to claim 1, wherein the controller:

calculates logical address range by aligning logical address of data to be outputted from the first memory area into the second management unit;

counts data of the first management unit which is included in the logical address range and is stored in the first and second memory areas;

executes the second processing if the sum of counted data is less than a predetermined threshold value; and

executes the third processing if the sum of counted data is equal to the predetermined threshold value or more.

11. The semiconductor storage device according to claim 4, wherein the nonvolatile semiconductor memory needs to perform erasing of data in an area of the third unit before rewriting of data in an area of the second unit included in the area of the third unit.

12. The semiconductor storage device according to claim 11, wherein in the second processing, the controller:

writes new data of the first management unit, which is outputted from the first memory area, in empty areas of the second unit in the second memory area;

sets old data stored in the second memory area invalid if logical address of the new data corresponds to logical address of the old data;

treats the new data as valid data which has priority over the old data; and

treats the old data as invalid data which is ignored by referring to the new data.

13. The semiconductor storage device according to claim 12, wherein the controller executes the fourth and fifth processing if a sum of areas of the third unit occupied by a plurality of valid and invalid data stored in the second memory area exceeds a permissible range.

14. The semiconductor storage device according to claim 13, wherein in the fourth processing, the controller:

detects an area of the third unit having the oldest writing order in the second memory area; and

selects each valid data of the first management unit stored in the detected area of the third unit.

15. The semiconductor storage device according to claim 13, wherein in the fourth processing, the controller:

calculates logical address range by aligning logical address of valid data into the second management unit for each area of the third unit in the second memory area;

counts valid data of the first management unit which is included in the logical address range and is stored in the second memory area;

sums the number of counted valid data for each area of the third unit in the second memory area;

detects an area of the third unit having the largest sum of valid data; and

selects each valid data of the first management unit stored in the detected area of the third unit.

16. The semiconductor storage device according to claim 13, wherein in the fourth processing, the controller:

counts invalid data of the first management unit for each area of the third unit in the second memory area;

detects an area of the third unit having the smallest number of counted invalid data; and

selects each valid data of the first management unit stored in the detected area of the third unit.

17. The semiconductor storage device according to claim 12, wherein the controller:

judges whether a sum of invalid data in the second memory area exceeds a predetermined threshold value;

counts invalid data of the first management unit for each area of the third unit in the second memory area;

selects valid data in areas of the third unit in order from the one with the largest number of invalid data;

copies the selected valid data in a first area of the third unit, the first area has empty areas of the second unit;

allocates the first area to the second memory area after copying the selected valid data therein; and

releases a second area of the third unit from the second memory area, the second area has no valid data as a result of copying the selected valid data in the first area.

18. The semiconductor storage device according to claim 11, wherein in the third processing, the controller:

writes new data of the second management unit, which is outputted from the first memory area, in empty areas of the second unit in the third memory area;

sets old data stored in the third memory area invalid if logical address of the new data corresponds to logical address of the old data;

treats the new data as valid data which has priority over the old data; and

treats the old data as invalid data which is ignored by referring to the new data.

19. The semiconductor storage device according to claim 18, wherein the controller:

judges whether a sum of invalid data in the third memory area exceeds a predetermined threshold value;

counts invalid data of the second management unit for each area of the third unit in the third memory area;

selects valid data in areas of the third unit in order from the one with the largest number of invalid data;

copies the selected valid data in a first area of the third unit, the first area has empty areas of the second unit;

allocates the first area to the third memory area after copying the selected valid data therein; and

releases a second area of the third unit from the third memory area, the second area has no valid data as a result of copying the selected valid data in the first area, wherein

the second management unit is less than the third unit.

20. The semiconductor storage device according to claim 1, wherein the second unit is twice or larger natural number times as large as the first management unit.

21. The semiconductor storage device according to claim 1, wherein

the first management unit is twice or larger natural number times as large as the second unit, and

the third unit is twice or larger natural number times as large as the first management unit.

22. The semiconductor storage device according to claim 1, wherein the third unit is twice or larger natural number times as large as the second management unit.

23. The semiconductor storage device according to claim 1, wherein the second management unit is twice or larger natural number times as large as the third unit.

24. The semiconductor storage device according to claim 1, wherein a size of the first management unit is equal to that of the second unit.

25. The semiconductor storage device according to claim 1, wherein a size of the second management unit is equal to that of the third unit.

26. The semiconductor storage device according to claim 12, wherein the controller invalidates an area of the third unit in which all areas of the second unit are invalidated.

27. The semiconductor storage device according to claim 18, wherein the controller invalidates an area of the third unit in which all areas of the second unit are invalidated.

28. The semiconductor storage device according to claim 1, wherein the volatile semiconductor memory is a DRAM and the nonvolatile semiconductor memory is a NAND type flash memory.

29. The semiconductor storage device according to claim 1, wherein the nonvolatile semiconductor memory includes MLC (Multi Level Cell) areas of the third unit in which multi bits data are programmed to one memory cell.

30. A method of controlling a semiconductor storage device, the semiconductor storage device having a first memory area configured in a volatile semiconductor memory which performs writing of data by a first unit or less;

and second and third memory areas configured in a nonvolatile semiconductor memory which performs writing of data by a second unit and performs erasing of data by a third unit, the third unit being twice or larger natural number times as large as the second unit, comprising;

accessing to the semiconductor storage device by the first unit for writing data;

executing a first processing for storing a plurality of data by the first unit in the first memory area;

executing a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, the first management unit being twice or larger natural number times as large as the first unit and being less than the third unit; and

executing a third processing for storing data outputted from the first memory area by a second management unit in the third memory area, the second management unit being twice or larger natural number times as large as the first management unit.

31. The method according to claim 30, wherein the second processing includes:

reading data which composes data of the first management unit and is not stored in the first memory area from at least one of the second and third memory areas; and

merging data stored in the first memory area and data read from at least one of the second and third memory areas into data of the first management unit.

32. The method according to claim 30, wherein the third processing includes:

reading data which composes data of the second management unit and is not stored in the first memory area from at least one of the second and third memory areas; and

merging data stored in the first memory area and data read from at least one of the second and third memory areas into data of the second management unit.

33. The method according to claim 30, further comprising:

executing a fourth processing for selecting data of the first management unit to be outputted from the second memory area; and

executing a fifth processing for storing data including the selected data by the second management unit in the third memory area.

34. The method according to claim 33, wherein the fifth processing includes,

calculating logical address range by aligning logical address of the selected data into the second management unit;

reading data included in the logical address range from at least one of the first, second, and third memory areas; and

merging the selected data and data read from at least one of the first, second, and third memory areas into data of the second management unit.

35. The method according to claim 30, wherein the second and third memory areas share the same nonvolatile semiconductor memory, and further comprising:

allocating areas of the third unit to the second and third memory areas respectively.

36. The method according to claim 30, wherein the first processing includes:

calculating logical address range by aligning logical address of data inputted to the semiconductor storage device into the first management unit; and

storing data of the first unit in an area of the first management unit corresponding to the logical address range in the first memory area.

37. The method according to claim 36, wherein the first processing includes judging whether the logical address range is available for storing data of the first unit in the first memory area, and at least one of the second and third processing is executed if the logical address range is not available.

38. The method according to claim 30, further comprising:

calculating logical address range by aligning logical address of data to be outputted from the first memory area into the second management unit; and

counting data of the first management unit which is included in the logical address range and is stored in the first memory area, wherein

the second processing is executed if the sum of counted data is less than a predetermined threshold value, and

the third processing is executed if the sum of counted data is equal to the predetermined threshold value or more.

39. The method according to claim 30, further comprising:

calculating logical address range by aligning logical address of data to be outputted from the first memory area into the second management unit; and

counting data of the first management unit which is included in the logical address range and is stored in the first and second memory areas, wherein

the second processing is executed if the sum of counted data is less than a predetermined threshold value, and

the third processing executed if the sum of counted data is equal to the predetermined threshold value or more.

40. The method according to claim 33, wherein the nonvolatile semiconductor memory needs to perform erasing of data in an area of the third unit before rewriting of data in an area of the second unit included in the area of the third unit.

41. The method according to claim 40, wherein the second processing includes:

writing new data of the first management unit, which is outputted from the first memory area, in empty areas of the second unit in the second memory area;

setting old data stored in the second memory area invalid if logical address of the new data corresponds to logical address of the old data;

treating the new data as valid data which has priority over the old data; and

treating the old data as invalid data which is ignored by referring to the new data.

42. The method according to claim 41, wherein the fourth and fifth processing are executed if a sum of areas of the third unit occupied by a plurality of valid and invalid data stored in the second memory area exceeds a permissible range.

43. The method according to claim 42, wherein the fourth processing includes:

detecting an area of the third unit having the oldest writing order in the second memory area; and

selecting each valid data of the first management unit stored in the detected area of the third unit.

44. The method according to claim 42, wherein the fourth processing includes:

calculating logical address range by aligning logical address of valid data into the second management unit for each area of the third unit in the second memory area;

counting valid data of the first management unit which is included in the logical address range and is stored in the second memory area;

summing the number of counted valid data for each area of the third unit in the second memory area;

detecting an area of the third unit having the largest sum of valid data; and

selecting each valid data of the first management unit stored in the detected area of the third unit.

45. The method according to claim 42, wherein the fourth processing includes:

counting invalid data of the first management unit for each area of the third unit in the second memory area;

detecting an area of the third unit having the smallest number of counted invalid data; and

selecting each valid data of the first management unit stored in the detected area of the third unit.

46. The method according to claim 41, further comprising:

judging whether a sum of invalid data in the second memory area exceeds a predetermined threshold value;

counting invalid data of the first management unit for each area of the third unit in the second memory area;

selecting valid data in areas of the third unit in order from the one with the largest number of invalid data;

copying the selected valid data in a first area of the third unit, the first area has empty areas of the second unit;

allocating the first area to the second memory area after copying the selected valid data therein; and

releasing a second area of the third unit from the second memory area, the second area has no valid data as a result of copying the selected valid data in the first area.

47. The method according to claim 40, wherein the third processing includes:

writing new data of the second management unit, which is outputted from the first memory area, in empty areas of the second unit in the third memory area;

setting old data stored in the third memory area invalid if logical address of the new data corresponds to logical address of the old data;

treating the new data as valid data which has priority over the old data; and

treating the old data as invalid data which is ignored by referring to the new data.

48. The method according to claim 47, further comprising:

judging whether a sum of invalid data in the third memory area exceeds a predetermined threshold value;

counting invalid data of the second management unit for each area of the third unit in the third memory area;

selecting valid data in areas of the third unit in order from the one with the largest number of invalid data;

copying the selected valid data in a first area of the third unit, the first area has empty areas of the second unit;

allocating the first area to the third memory area after copying the selected valid data therein; and

releasing a second area of the third unit from the third memory area, the second area has no valid data as a result of copying the selected valid data in the first area, wherein

the second management unit is less than the third unit.

49. The method according to claim 30, wherein the second unit is twice or larger natural number times as large as the first management unit.

50. The method according to claim 30, wherein

the first management unit is twice or larger natural number times as large as the second unit, and

the third unit is twice or larger natural number times as large as the first management unit.

51. The method according to claim 30, wherein the third unit is twice or larger natural number times as large as the second management unit.

52. The method according to claim 30, wherein the second management unit is twice or larger natural number times as large as the third unit.

53. The method according to claim 30, wherein a size of the first management unit is equal to that of the second unit.

54. The method according to claim 30, wherein a size of the second management unit is equal to that of the third unit.

55. The method according to claim 41, further comprising:

invalidating an area of the third unit in which all areas of the second unit are invalidated.

56. The method according to claim 47, further comprising:

invalidating an area of the third unit in which all areas of the second unit are invalidated.

57. The method according to claim 30, wherein the volatile semiconductor memory is a DRAM and the nonvolatile semiconductor memory is a NAND type flash memory.

58. The method according to claim 30, wherein the nonvolatile semiconductor memory includes MLC (Multi Level Cell) areas of the third unit in which multi bits data are programmed to one memory cell.

59. An information processing apparatus comprising:

a CPU;

a main memory; and

a semiconductor storage device, wherein

the semiconductor storage device includes;

a first memory area configured in a volatile semiconductor memory which performs writing of data by a first unit or less, the first unit being an access unit to the semiconductor storage device;

second and third memory areas configured in a nonvolatile semiconductor memory which performs writing of data by a second unit and performs erasing of data by a third unit, the third unit being twice or larger natural number times as large as the second unit; and

a controller executing;

a first processing for storing a plurality of data by the first unit in the first memory area;

a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, the first management unit being twice or larger natural number times as large as the first unit and being less than the third unit; and

a third processing for storing data outputted from the first memory area by a second management unit in the third memory area, the second management unit being twice or larger natural number times as large as the first management unit.

60. The information processing apparatus according to claim 59, the semiconductor storage device is controlled through an ATA interface.

61. The information processing apparatus according to claim 60, wherein the semiconductor storage device is accessed using a logical address of the first unit.

62. The information processing apparatus according to claim 59, wherein the semiconductor storage device stores an operating system executed by the CPU.

63. The information processing apparatus according to claim 62, wherein the main memory temporary stores the operating system loaded from the semiconductor storage device.

64. The information processing apparatus according to claim 63, wherein the main memory is a DRAM directory accessed by the CPU.

65. The information processing apparatus according to claim 59, wherein in the second processing, the controller:

reads data which composes data of the first management unit and is not stored in the first memory area from at least one of the second and third memory areas; and

merges data stored in the first memory area and data read from at least one of the second and third memory areas into data of the first management unit.

66. The information processing apparatus according to claim 59, wherein in the third processing, the controller:

reads data which composes data of the second management unit and is not stored in the first memory area from at least one of the second and third memory areas; and

merges data stored in the first memory area and data read from at least one of the second and third memory areas into data of the second management unit.

67. The information processing apparatus according to claim 59, wherein the controller executes:

a fourth processing for selecting data of the first management unit to be outputted from the second memory area; and

a fifth processing for storing data including the selected data by the second management unit in the third memory area.

68. The information processing apparatus to claim 67, wherein in the fifth processing, the controller:

calculates logical address range by aligning logical address of the selected data into the second management unit;

reads data included in the logical address range from at least one of the first, second, and third memory areas; and

merges the selected data and data read from at least one of the first, second, and third memory areas into data of the second management unit.

69. The information processing apparatus according to claim 59, wherein

the second and third memory areas share the same nonvolatile semiconductor memory, and

the controller allocates areas of the third unit to the second and third memory areas respectively.

70. The information processing apparatus according to claim 59, wherein in the first processing, the controller:

calculates logical address range by aligning logical address of data inputted to the semiconductor storage device into the first management unit; and

stores data of the first unit in an area of the first management unit corresponding to the logical address range in the first memory area.

71. The information processing apparatus according to claim 70, wherein in the first processing, the controller:

judges whether the logical address range is available for storing data of the first unit in the first memory area; and

executes at least one of the second and third processing if the logical address range is not available.

72. The information processing apparatus according to claim 59, wherein the controller:

calculates logical address range by aligning logical address of data to be outputted from the first memory area into the second management unit;

counts data of the first management unit which is included in the logical address range and is stored in the first memory area;

executes the second processing if the sum of counted data is less than a predetermined threshold value; and

executes the third processing if the sum of counted data is equal to the predetermined threshold value or more.

73. The information processing apparatus according to claim 59, wherein the controller:

calculates logical address range by aligning logical address of data to be outputted from the first memory area into the second management unit;

counts data of the first management unit which is included in the logical address range and is stored in the first and second memory areas;

executes the second processing if the sum of counted data is less than a predetermined threshold value; and

executes the third processing if the sum of counted data is equal to the predetermined threshold value or more.

74. The information processing apparatus according to claim 67, wherein the nonvolatile semiconductor memory needs to perform erasing of data in an area of the third unit before rewriting of data in an area of the second unit included in the area of the third unit.

75. The information processing apparatus according to claim 74, wherein in the second processing, the controller:

writes new data of the first management unit, which is outputted from the first memory area, in empty areas of the second unit in the second memory area;

sets old data stored in the second memory area invalid if logical address of the new data corresponds to logical address of the old data;

treats the new data as valid data which has priority over the old data; and

treats the old data as invalid data which is ignored by referring to the new data.

76. The information processing apparatus according to claim 75, wherein the controller executes the fourth and fifth processing if a sum of areas of the third unit occupied by a plurality of valid and invalid data stored in the second memory area exceeds a permissible range.

77. The information processing apparatus according to claim 76, wherein in the fourth processing, the controller:

detects an area of the third unit having the oldest writing order in the second memory area; and

selects each valid data of the first management unit stored in the detected area of the third unit.

78. The information processing apparatus according to claim 76, wherein in the fourth processing, the controller:

calculates logical address range by aligning logical address of valid data into the second management unit for each area of the third unit in the second memory area;

counts valid data of the first management unit which is included in the logical address range and is stored in the second memory area;

sums the number of counted valid data for each area of the third unit in the second memory area;

detects an area of the third unit having the largest sum of valid data; and

selects each valid data of the first management unit stored in the detected area of the third unit.

79. The information processing apparatus according to claim 76, wherein in the fourth processing, the controller:

counts invalid data of the first management unit for each area of the third unit in the second memory area;

detects an area of the third unit having the smallest number of counted invalid data; and

selects each valid data of the first management unit stored in the detected area of the third unit.

80. The information processing apparatus according to claim 75, wherein the controller:

judges whether a sum of invalid data in the second memory area exceeds a predetermined threshold value;

counts invalid data of the first management unit for each area of the third unit in the second memory area;

selects valid data in areas of the third unit in order from the one with the largest number of invalid data;

copies the selected valid data in a first area of the third unit, the first area has empty areas of the second unit;

allocates the first area to the second memory area after copying the selected valid data therein; and

releases a second area of the third unit from the second memory area, the second area has no valid data as a result of copying the selected valid data in the first area.

81. The information processing apparatus according to claim 74, wherein in the third processing, the controller:

writes new data of the second management unit, which is outputted from the first memory area, in empty areas of the second unit in the third memory area;

sets old data stored in the third memory area invalid if logical address of the new data corresponds to logical address of the old data;

treats the new data as valid data which has priority over the old data; and

treats the old data as invalid data which is ignored by referring to the new data.

82. The information processing apparatus according to claim 81, wherein the controller:

judges whether a sum of invalid data in the third memory area exceeds a predetermined threshold value;

counts invalid data of the second management unit for each area of the third unit in the third memory area;

selects valid data in areas of the third unit in order from the one with the largest number of invalid data;

copies the selected valid data in a first area of the third unit, the first area has empty areas of the second unit;

allocates the first area to the third memory area after copying the selected valid data therein;

releases a second area of the third unit from the third memory area, the second area has no valid data as a result of copying the selected valid data in the first area, and wherein

the second management unit is less than the third unit.

83. The information processing apparatus according to claim 59, wherein the second unit is twice or larger natural number times as large as the first management unit.

84. The information processing apparatus according to claim 59, wherein

the first management unit is twice or larger natural number times as large as the second unit, and

the third unit is twice or larger natural number times as large as the first management unit.

85. The information processing apparatus according to claim 59, wherein the third unit is twice or larger natural number times as large as the second management unit.

86. The information processing apparatus according to claim 59, wherein the second management unit is twice or larger natural number times as large as the third unit.

87. The information processing apparatus according to claim 59, wherein a size of the first management unit is equal to that of the second unit.

88. The information processing apparatus according to claim 59, wherein a size of the second management unit is equal to that of the third unit.

89. The information processing apparatus according to claim 75, wherein the controller invalidates an area of the third unit in which all areas of the second unit are invalidated.

90. The information processing apparatus according to claim 81, wherein the controller invalidates an area of the third unit in which all areas of the second unit are invalidated.

91. The information processing apparatus according to claim 59, wherein the volatile semiconductor memory is a DRAM and the nonvolatile semiconductor memory is a NAND type flash memory.

92. The information processing apparatus according to claim 59, wherein the nonvolatile semiconductor memory includes MLC (Multi Level Cell) areas of the third unit in which multi bits data are programmed to one memory cell.

93. A controller, which controls a first memory area configured in a volatile semiconductor memory which performs writing of data by a first unit or less, the first unit being an access unit to the semiconductor storage device;

and second and third memory areas configured in a nonvolatile semiconductor memory which performs writing of data by a second unit and performs erasing of data by a third unit, the third unit being twice or larger natural number times as large as the second unit, comprising;

a data control unit which executes;

a first processing for storing a plurality of data by the first unit in the first memory area;

a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, the first management unit being twice or larger natural number times as large as the first unit and being less than the third unit; and

a third processing for storing data outputted from the first memory area by a second management unit in the third memory area, the second management unit being twice or larger natural number times as large as the first management unit.

94. The controller according to claim 93, further comprising:

an ATA command processing unit which performs data transfer to the first memory area in cooperation with the data control unit.

95. The controller according to claim 93, further comprising:

a security control unit which controls security information in cooperation with the data control unit.

96. The controller according to claim 93, wherein in the second processing, the data control unit:

reads data which composes data of the first management unit and is not stored in the first memory area from at least one of the second and third memory areas; and

merges data stored in the first memory area and data read from at least one of the second and third memory areas into data of the first management unit.

97. The controller according to claim 93, wherein in the third processing, the data control unit:

reads data which composes data of the second management unit and is not stored in the first memory area from at least one of the second and third memory areas; and

merges data stored in the first memory area and data read from at least one of the second and third memory areas into data of the second management unit.

98. The controller according to claim 93, wherein the data control unit:

a fourth processing for selecting data of the first management unit to be outputted from the second memory area; and

a fifth processing for storing data including the selected data by the second management unit in the third memory area.

99. The controller according to claim 98, wherein in the fifth processing, the data control unit:

calculates logical address range by aligning logical address of the selected data into the second management unit;

reads data included in the logical address range from at least one of the first, second, and third memory areas; and

merges the selected data and data read from at least one of the first, second, and third memory areas into data of the second management unit.

100. The controller according to claim 93, wherein

the second and third memory areas share the same nonvolatile semiconductor memory, and

the data control unit allocates areas of the third unit to the second and third memory areas respectively.

101. The controller according to claim 93, wherein in the first processing, the data control unit:

calculates logical address range by aligning logical address of data inputted to the semiconductor storage device into the first management unit; and

stores data of the first unit in an area of the first management unit corresponding to the logical address range in the first memory area.

102. The controller according to claim 101, wherein in the first processing, the data control unit:

judges whether the logical address range is available for storing data of the first unit in the first memory area; and

executes at least one of the second and third processing if the logical address range is not available.

103. The controller according to claim 93, wherein the data control unit:

calculates logical address range by aligning logical address of data to be outputted from the first memory area into the second management unit;

counts data of the first management unit which is included in the logical address range and is stored in the first memory area;

executes the second processing if the sum of counted data is less than a predetermined threshold value; and

executes the third processing if the sum of counted data is equal to the predetermined threshold value or more.

104. The controller according to claim 93, wherein the data control unit:

calculates logical address range by aligning logical address of data to be outputted from the first memory area into the second management unit;

counts data of the first management unit which is included in the logical address range and is stored in the first and second memory areas;

executes the second processing if the sum of counted data is less than a predetermined threshold value; and

executes the third processing if the sum of counted data is equal to the predetermined threshold value or more.

105. The controller according to claim 98, wherein the nonvolatile semiconductor memory needs to perform erasing of data in an area of the third unit before rewriting of data in an area of the second unit included in the area of the third unit.

106. The controller according to claim 105, wherein in the second processing, the data control unit:

writes new data of the first management unit, which is outputted from the first memory area, in empty areas of the second unit in the second memory area;

sets old data stored in the second memory area invalid if logical address of the new data corresponds to logical address of the old data;

treats the new data as valid data which has priority over the old data; and

treats the old data as invalid data which is ignored by referring to the new data.

107. The controller according to claim 106, wherein the data control unit executes the fourth and fifth processing if a sum of areas of the third unit occupied by a plurality of valid and invalid data stored in the second memory area exceeds a permissible range.

108. The controller according to claim 107, wherein in the fourth processing, the data control unit:

detects an area of the third unit having the oldest writing order in the second memory area; and

selects each valid data of the first management unit stored in the detected area of the third unit.

109. The controller device according to claim 107, wherein in the fourth processing, the data control unit:

calculates logical address range by aligning logical address of valid data into the second management unit for each area of the third unit in the second memory area;

counts valid data of the first management unit which is included in the logical address range and is stored in the second memory area;

sums the number of counted valid data for each area of the third unit in the second memory area;

detects an area of the third unit having the largest sum of valid data; and

selects each valid data of the first management unit stored in the detected area of the third unit.

110. The controller according to claim 107, wherein in the fourth processing, the data control unit:

counts invalid data of the first management unit for each area of the third unit in the second memory area;

detects an area of the third unit having the smallest number of counted invalid data; and

selects each valid data of the first management unit stored in the detected area of the third unit.

111. The controller according to claim 106, wherein the data control unit:

judges whether a sum of invalid data in the second memory area exceeds a predetermined threshold value;

counts invalid data of the first management unit for each area of the third unit in the second memory area;

selects valid data in areas of the third unit in order from the one with the largest number of invalid data;

copies the selected valid data in a first area of the third unit, the first area has empty areas of the second unit;

allocates the first area to the second memory area after copying the selected valid data therein; and

releases a second area of the third unit from the second memory area, the second area has no valid data as a result of copying the selected valid data in the first area.

112. The controller according to claim 105, wherein in the third processing, the data control unit:

writes new data of the second management unit, which is outputted from the first memory area, in empty areas of the second unit in the third memory area;

sets old data stored in the third memory area invalid if logical address of the new data corresponds to logical address of the old data;

treats the new data as valid data which has priority over the old data; and

treats the old data as invalid data which is ignored by referring to the new data.

113. The controller according to claim 112, wherein the data control unit:

judges whether a sum of invalid data in the third memory area exceeds a predetermined threshold value;

counts invalid data of the second management unit for each area of the third unit in the third memory area;

selects valid data in areas of the third unit in order from the one with the largest number of invalid data;

copies the selected valid data in a first area of the third unit, the first area has empty areas of the second unit;

allocates the first area to the third memory area after copying the selected valid data therein; and

releases a second area of the third unit from the third memory area, the second area has no valid data as a result of copying the selected valid data in the first area, wherein

the second management unit is less than the third unit.

114. The controller according to claim 93, wherein the second unit is twice or larger natural number times as large as the first management unit.

115. The controller according to claim 93, wherein

the first management unit is twice or larger natural number times as large as the second unit, and

the third unit is twice or larger natural number times as large as the first management unit.

116. The controller according to claim 93, wherein the third unit is twice or larger natural number times as large as the second management unit.

117. The controller according to claim 93, wherein the second management unit is twice or larger natural number times as large as the third unit.

118. The controller according to claim 93, wherein a size of the first management unit is equal to that of the second unit.

119. The controller according to claim 93, wherein a size of the second management unit is equal to that of the third unit.

120. The controller according to claim 106, wherein the data control unit invalidates an area of the third unit in which all areas of the second unit are invalidated.

121. The controller according to claim 112, wherein the data control unit invalidates an area of the third unit in which all areas of the second unit are invalidated.