MEMORY INTERLEAVE FOR HETEROGENEOUS COMPUTING
First Claim
1. A system comprising:
- a memory;
a first compute element that issues cache-block oriented access requests to said memory;
a second compute element that issues sub-cache-block oriented access requests to said memory; and
a memory interleave system that interleaves the cache-block oriented and sub-cache-block oriented access requests.
10 Assignments
0 Petitions
Accused Products
Abstract
A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by heterogeneous compute elements in different ways, such as via cache-block accesses by certain compute elements and via non-cache-block accesses by certain other compute elements. The heterogeneous computing system may comprise one or more cache-block oriented compute elements and one or more non-cache-block oriented compute elements that share access to a common main memory. The cache-block oriented compute elements access the memory via cache-block accesses (e.g., 64 bytes, per access), while the non-cache-block oriented compute elements access memory via sub-cache-block accesses (e.g., 8 bytes, per access). A memory interleave system is provided to optimize the interleaving across the system'"'"'s memory banks to minimize hot spots resulting from the cache-block oriented and non-cache-block oriented accesses of the heterogeneous computing system.
125 Citations
60 Claims
-
1. A system comprising:
-
a memory; a first compute element that issues cache-block oriented access requests to said memory; a second compute element that issues sub-cache-block oriented access requests to said memory; and a memory interleave system that interleaves the cache-block oriented and sub-cache-block oriented access requests. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A system comprising:
-
a memory; a first compute element that issues physical address requests for accessing said memory; a second compute element that issues virtual address requests for accessing said memory; and a memory interleave system that receives the physical address requests from the first compute element and the virtual address requests from the second compute element, and performs memory interleaving of the requests without requiring the received virtual address requests to be translated into a physical address. - View Dependent Claims (11, 12, 13, 14, 15, 16)
-
-
17. A system comprising:
-
a memory; a plurality of memory controllers for said memory; a first compute element that issues physical addresses for cache-block oriented access requests to said memory; a second compute element that issues virtual addresses for sub-cache-block oriented access requests to said memory, wherein said first and second compute elements share a common physical and virtual address space of the memory; a memory interleave system that receives the physical address for the cache-block oriented access requests issued by the first compute element and receives the virtual addresses for the sub-cache-block oriented access requests issued by the second compute element, and said memory interleave system determines, for each of the received cache-block oriented and sub-cache-block oriented access requests, one of the plurality of memory controllers to direct the access request for interleaving the cache-block oriented and sub-cache-block oriented access requests. - View Dependent Claims (18, 19, 20, 21)
-
-
22. A system comprising:
-
non-sequential access memory; a cache-access path in which cache-block data is communicated between said non-sequential access memory and a cache memory; and a direct-access path in which sub-cache-block data is communicated to/from said non-sequential access memory; and a memory interleave system for interleaving accesses to said non-sequential access memory via the cache-access path and the direct-access path to minimize hot spots within said non-sequential access memory. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
-
-
36. A memory interleave system comprising:
-
an interface for receiving cache-block oriented memory access requests; an interface for receiving sub-cache-block oriented memory access requests; logic for processing the received cache-block oriented and sub-cache-block oriented memory access requests for interleaving the received memory access requests to minimize hot spots within a memory. - View Dependent Claims (37, 38, 39, 40, 41, 42, 43)
-
-
44. A method for performing memory interleaving, said method comprising:
-
receiving, by a memory interleave system, a cache-block oriented memory access request from a first compute element of a system; receiving, by the memory interleave system, a sub-cache-block oriented memory access request from a second compute element of the system; and performing memory interleaving, by the memory interleave system, for the received cache-block oriented and sub-cache-block oriented memory access requests. - View Dependent Claims (45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57)
-
-
58. A method for performing memory interleaving comprising:
-
performing, in a first level of a two-level interleaving scheme, interleaving across full cache lines of a memory; and performing, in a second level of the two-level interleaving scheme, interleaving across sub-cache lines of the memory. - View Dependent Claims (59, 60)
-
Specification