METHOD AND APPARATUS FOR TESTING DELAY FAULTS

• US 20100037111A1
• Filed: 08/06/2008
• Published: 02/11/2010
• Est. Priority Date: 08/06/2008
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Molyneaux, Robert F., Woodling, Kevin D., Ziaja, Thomas A.
• Granted Patent: US 8,074,133 B2
• Time in Patent Office: Days
• US Class Current: 714/744
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G06F 11/24 Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests

Abstract

An apparatus or method for testing of a SOC processor device may minimize interference that is caused by interfacing a comparatively low-speed testing device with the high-speed processor during testing. Implementations may gate the input clock signal at the clock input to each domain of the SOC processor device rather than at the output of the PLL clock. The gating of the clock signal to each domain may then be controlled by clock stop signals generated by the testing device and sent to the individual domains of the processor device. Gating the clock signal at the domain may provide a more natural state for the circuit during testing as well as allow the test control unit to test the different domains of the SOC device individually.

Claims

1. A method for testing at least one domain of a processor device including a plurality of domains, the method comprising:

controlling a gate coupled to the at least one domain, wherein the gate is configured to control propagation of a clock signal into the at least one domain without affecting propagation of the clock signal to other domains of the processor device.

2. The method of claim 1 wherein in the controlling operation further comprises:

transmitting a signal to open the gate and allow the clock signal to propagate into the at least one domain;

maintaining the open gate for a desired number of clock pulses; and

transmitting a signal to close the gate and prevent the clock signal from propagating into the at least one domain.

3. The method of claim 1 further comprising:

loading a first value into a counter, the first value indicative of a desired number of clock pulses.

4. The method of claim 3 wherein the controlling operation further comprises:

transmitting a signal to open the gate;

decrementing the counter from the first value upon opening the gate; and

transmitting a signal to close the gate when the counter reaches zero.

5. The method of claim 4 wherein the decrementing operation further comprises:

decrementing the counter at a same frequency as the clock signal.

6. The method of claim 4 further comprising:

loading a second value into the counter after the gate is closed;

opening a second gate coupled to a second domain of the plurality of domains, wherein the second gate is configured to control propagation of the clock signal into the second domain without affecting propagation of the clock signal to other domains of the processor device;

decrementing the counter from the second value upon opening the second gate; and

closing the second gate when the counter reaches zero.

7. The method of claim 1 wherein controlling the gate comprises:

controlling a plurality of gates, the plurality of gates each coupled to a respective domain of the plurality of domains of the processor device, wherein the plurality of gates are configured to control propagation of a clock signal into the respective domains of the processor device.

8. The method of claim 7 wherein the controlling operation further comprises:

transmitting a signal to the plurality of gates to close the plurality of gates;

transmitting a signal to open at least one gate of the plurality of gates while maintaining remaining gates closed;

maintaining the at least one gate open for a desired number of clock pulses; and

transmitting a signal to close the at least one gate upon occurrence of the desired number of clock pulses with the at least one gate open.

9. The method of claim 7 wherein the controlling operation further comprises:

transmitting a signal to the plurality of gates to close the plurality of gates;

transmitting a signal to open multiple gates of the plurality of gates while maintaining remaining gates closed;

maintaining the multiple gates open for a desired number of clock pulses; and

transmitting a signal to close the multiple gates upon occurrence of the desired number of clock pulses with the at least one gate open.

10. The method of claim 1 further comprising:

providing a test pattern to the processor device; and

providing a scan enable signal to the processor device, wherein, upon receipt of the scan enable signal, the processor scans in the test pattern.

11. A system for testing at least one domain of a processor device including a plurality of domains, the system comprising:

a clock gate controller configured to control at least one gate, wherein the at least one gate is coupled to the at least one domain and is configured to control propagation of a clock signal into the at least one domain without affecting propagation of the clock signal to other domains of the processor device.

12. The system of claim 11 further comprising:

a pattern generator configured to provide a test pattern to the processor device; and

a counter operably connected to the clock gate controller.

13. The system of claim 12 wherein the counter decrements from a provided value, the provided value indicative of a desired number of clock pulses.

14. The system of claim 13 wherein the clock gate controller closes the gate coupled to the at least one domain when the counter reaches zero.

15. The system of claim 11 wherein the clock gate controller is configured to control a plurality of gates, the plurality of gates each coupled to a respective domain of the plurality of domains of the processor device.

16. A computer-implemented system for testing at least one domain of a processor device including a plurality of domains, the system comprising:

a clock controller module configured to control at least one gate, wherein the at least one gate is coupled to the at least one domain and is configured to control propagation of a clock signal into the at least one domain without affecting propagation of the clock signal into other domains of the processor device.

17. The system of claim 16 further comprising:

a pattern generator module configured to provide a test pattern to the processor device; and

a counter module operably connected to the clock gate controller module.

18. The system of claim 17 wherein the counter module decrements from a provided value, the value provided indicative of a desired number of clock pulses.

19. The system of claim 18 wherein the clock gate controller module closes the gate coupled to the at least one domain when the counter reaches zero.

20. The system of claim 16 wherein the clock gate controller module is configured to control a plurality of gates, the plurality of gates each coupled to a respective domain of the plurality of domains of the processor device.