M/H FRAME ENCODING AND DECODING TECHNIQUES FOR 8VSB DTV BROADCASTING SYSTEMS

• US 20100037120A1
• Filed: 07/31/2009
• Published: 02/11/2010
• Est. Priority Date: 08/05/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LIMBERG, Allen LeRoy
• Granted Patent: US 8,271,849 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: H03M 13/253 with concatenated codes
• CPC Class Codes: H03M 13/256 with trellis coding, e.g. with convolutional codes and TCM
• CPC Class Codes: H03M 13/2936 comprising an outer Reed-Solomon code and an inner convolutional code
• CPC Class Codes: H03M 13/6538 ATSC VBS systems

Abstract

Modification of the prior-art M/H system to better suit transmission of internet-protocol (IP) transport packets includes a standard codeword length for a plurality of various options for transverse Reed-Solomon coding of M/H data, which options offer different degrees of forward-error-correction capability. A 235-byte standard codeword length for TRS coding of M/H data allows extending the FIC-Chunks in the Fast Information Channel signaling to double length so as to substantially increase the capability of such signaling to convey information concerning M/H services. In some transmitter apparatus constructed in accordance with aspect of the invention the TRS encoder in the M/H Frame encoder is modified for transmitting the parity bytes of TRS codewords before, rather than after, the data bytes of those TRS codewords.

Claims

1. An M/H pre-processor comprising:

an M/H Frame encoder connected for receiving an M/H service multiplex signal incorporating a number of M/H service signals employing internet protocol, randomizing the bits of each M/H service signal, effectively arraying each successive ensemble of bytes of said M/H service signal as so randomized by column and by row in a respective two-dimensional array of bytes called an RS Frame, transversely Reed-Solomon coding each column of bytes in each said respective two-dimensional array generating parity bytes to extend the length of said each column of bytes to a standard length for transverse Reed-Solomon codewords irrespective of their forward-error-correction capability, cyclic-redundancy-check (CRC) coding each successive row of bytes in each said respective two-dimensional array with extended columns of bytes to extend the length of said each successive row of bytes, and supplying said successive rows of bytes as thus extended as portions of an M/H Frame encoder output signal;

an improvement within said M/H pre-processor wherein said standard length for transverse Reed-Solomon codewords is the same for each said respective two-dimensional array independently of which of a plurality of permissible transverse Reed-Solomon coding algorithms with differing forward-error-correction capabilities is employed for encoding said respective two-dimensional array;

a block processor connected for receiving said M/H Frame encoder output signal, coding each of said portions of said M/H Frame encoder output signal as placed into serial-bit format in accordance with a selected one of possible outer convolutional coding procedures to generate a succession of bit-pairs of outer convolutional code, and block interleaving said bit-pairs of said outer convolutional code to generate interleaved outer convolutional coding;

a signaling encoder connected for generating signaling code defining a transmission parameter channel (TPC) and a fast information channel (FIC), said TPC signaling the forward-error-correction capability of the respective standard-length transverse Reed-Solomon coding for each said two-dimensional array of bytes called an RS Frame;

a Group formatter connected for combining said interleaved outer convolutional coding and said signaling code with null data to generate a signal that is subsequently pre-deinterleaved within said Group formatter to generate pre-deinterleaved M/H Group signal; and

a packet formatter for introducing portions of said pre-deinterleaved M/H Group signal into M/H encapsulating data packets that also include prescribed headers and portions of prescribed training signals.

2. The claim 1 M/H pre-processor wherein said standard length for transverse Reed-Solomon codewords is 235 bytes irrespective of which of said plurality of permissible transverse Reed-Solomon coding algorithms with differing forward-error-correction capabilities is employed for encoding said respective two-dimensional array.

3. The claim 1 M/H pre-processor wherein said plurality of permissible transverse Reed-Solomon coding algorithms with differing forward-error-correction capabilities includes a (235, 195) transverse Reed-Solomon coding algorithm.

4. The claim 1 M/H pre-processor wherein said plurality of permissible transverse Reed-Solomon coding algorithms with differing forward-error-correction capabilities includes a (235, 203) transverse Reed-Solomon coding algorithm.

5. The claim 1 M/H pre-processor wherein said M/H Frame encoder includes at least one Reed-Solomon encoder connected for generating systematic Reed-Solomon codes of said standard length, the parity bytes of each of said standard-length systematic Reed-Solomon codes being transmitted later in time than are the data bytes thereof.

6. The claim 1 M/H pre-processor wherein said M/H Frame encoder includes at least one Reed-Solomon encoder connected for generating non-systematic Reed-Solomon codes of said standard length.

7. The claim 1 M/H pre-processor wherein the data bytes in each of said standard-length non-systematic Reed-Solomon codes are transmitted later in time than are the parity bytes thereof.

8. The claim 1 M/H pre-processor wherein said signaling encoder is of a sort that generates a fast information channel (FIC) encodes extended FIC Chunks each having more bytes than 37 times the number of Groups in one-fifth of an M/H Frame.

9. The claim 1 M/H pre-processor wherein said block processor comprises an encoder for outer convolutional coding at one-third code rate.

10. An M/H pre-processor comprising:

an M/H Frame encoder connected for receiving an M/H service multiplex signal incorporating a number of M/H service signals employing internet protocol, randomizing the bits of each M/H service signal, effectively arraying each successive ensemble of bytes of said M/H service signal as so randomized by column and by row in a respective two-dimensional array of bytes called an RS Frame, transverse-Reed-Solomon coding each column of bytes in each said respective two-dimensional array generating parity bytes to extend the length of said each column of bytes, cyclic-redundancy-check (CRC) coding each successive row of bytes in each said respective two-dimensional array with extended columns of bytes to extend the length of said each successive row of bytes, and supplying said successive rows of bytes as thus extended as portions of an M/H Frame encoder output signal;

a block processor connected for receiving said M/H Frame encoder output signal, coding each of said portions of said M/H Frame encoder output signal as placed into serial-bit format in accordance with a selected one of possible outer convolutional coding procedures to generate a succession of bit-pairs of outer convolutional code, and block interleaving said bit-pairs of said outer convolutional code to generate interleaved outer convolutional coding;

a signaling encoder connected for generating signaling code defining a transmission parameter channel (TPC) and a fast information channel (FIC), said TPC signaling the forward-error-correction capability of the respective standard-length transverse Reed-Solomon coding for each said two-dimensional array of bytes called an RS Frame, said FIC encoding extended FIC-Chunks each having more bytes than 37 times the number of M/H Groups in one-fifth of an M/H Frame;

a Group formatter connected for combining said interleaved outer convolutional coding and said signaling code with null data to generate a signal that is subsequently pre-deinterleaved within said Group formatter to generate pre-deinterleaved M/H Group signal; and

a packet formatter for introducing portions of said pre-deinterleaved M/H Group signal into M/H encapsulating data packets that also include prescribed headers and portions of prescribed training signals.

11. An M/H pre-processor comprising:

an M/H Frame encoder connected for receiving an M/H service multiplex signal incorporating a number of M/H service signals employing internet protocol, randomizing the bits of each M/H service signal, effectively arraying each successive ensemble of bytes of said M/H service signal as so randomized by column and by row in a respective two-dimensional array of bytes called an RS Frame, transverse-Reed-Solomon coding each column of bytes in each said respective two-dimensional array generating parity bytes to extend the length of said each column of bytes, cyclic-redundancy-check (CRC) coding each successive row of bytes in each said respective two-dimensional array with extended columns of bytes to extend the length of said each successive row of bytes, and supplying said successive rows of bytes as thus extended as portions of an M/H Frame encoder output signal;

a block processor connected for receiving said M/H Frame encoder output signal, coding each of said portions of said M/H Frame encoder output signal as placed into serial-bit format in accordance with an outer convolutional coding procedure having a one-third code rate to generate a succession of bit-pairs of outer convolutional code, and block interleaving said bit-pairs of said outer convolutional code to generate interleaved outer convolutional coding;

a signaling encoder connected for generating signaling code defining a transmission parameter channel (TPC) and a fast information channel (FIC);

a Group formatter connected for combining said interleaved outer convolutional coding and said signaling code with null data to generate a signal that is subsequently pre-deinterleaved within said Group formatter to generate pre-deinterleaved M/H Group signal; and

a packet formatter for introducing portions of said pre-deinterleaved M/H Group signal into M/H encapsulating data packets that also include prescribed headers and portions of prescribed training signals.

12. Receiver apparatus for vestigial-sideband amplitude-modulated carrier waves transmitting trellis-coded digital information, portions of which trellis-coded digital information comprise serially concatenated convolutional coding of fields of two-dimensionally-coded internet-protocol (IP) digital data randomized bit by bit, the two-dimensional coding of the randomized IP digital data in each said field including transversal Reed-Solomon (TRS) coding of columns of bytes of said randomized IP digital data in that field and cyclic-redundancy-check (CRC) coding of rows of said bytes of said randomized IP digital data and of parity bytes of said TRS coding in a respective extension of that field, instructions for decoding each said field of two-dimensionally-coded randomized IP digital data being signaled by transmission parameter channel (TPC) information transmitted in portions of said trellis-coded digital information other than those said portions that comprise said serially concatenated convolutional coding of fields of two-dimensionally-coded randomized IP digital data randomized bit by bit, said receiver apparatus comprising:

a demodulator connected for receiving vestigial-sideband amplitude-modulated carrier waves transmitting trellis-coded digital information and for supplying trellis-coded digital information at baseband;

a decoder for quarter-rate parallel concatenated convolutional coding connected for reproducing randomized signaling information, by decoding parallel concatenated convolutional coding (PCCC) selected from the baseband trellis-coded digital information supplied from said demodulator;

a signaling bits de-randomizer connected for reproducing signaling information including said transmission parameter channel (TPC) information and also including Fast Information channel (FIC) information, by de-randomizing bits of said randomized signaling information;

a turbo decoder connected for reproducing rows of bytes of said fields of two-dimensionally-coded IP digital data randomized bit by bit, by decoding serial concatenated convolutional coding (SCCC) selected from the baseband trellis-coded digital information supplied from said demodulator, said decoding of SCCC selected from the baseband trellis-coded digital information supplied from said demodulator being directed in its performance responsive to said TPC information;

byte-organized memory connected for storing rows of bytes of said fields of two-dimensionally-coded randomized IP digital data as written thereto from said turbo decoder, said byte-organized memory connected for having successive columns of stored bytes read therefrom as respective TRS codewords after essentially all the rows of bytes of one of said fields of two-dimensionally coded randomized digital data have been stored within said byte-organized memory;

a decoder for CRC coding of each row of bytes in one of said fields of two-dimensionally coded randomized digital data as written thereto from said turbo decoder;

a byte-error-location-information register for temporarily storing the decoding results from said decoder for CRC coding, which decoding results are temporarily stored to provide byte-error-location information until completion of decoding of the TRS codewords in said one of said fields of two-dimensionally-coded randomized IP digital data;

a bank of respective decoders for Reed-Solomon coding of assorted types having different forward-error-correction capabilities, one of said decoders for Reed-Solomon coding being selected responsive to said TPC information for receiving said successive columns of stored bytes read from said byte-organized memory after essentially all the rows of bytes of one of said fields of two-dimensionally-coded randomized IP digital data have been stored therewithin, said selected one of said decoders for Reed-Solomon coding connected for receiving from said byte-error-location-information register the temporarily stored decoding results from said decoder for CRC coding and using them for locating possibly erroneous bytes in said TRS codewords, said selected one of said decoders for Reed-Solomon coding connected for writing corrected randomized digital data back into said byte-organized memory; and

a data de-randomizer connected for receiving rows of bytes of each of said fields of two-dimensionally-coded randomized IP digital data, as read from said byte-organized memory after forward error correction by said selected one of said decoders for Reed-Solomon coding is completed, and responding to reproduce said IP digital data.

13. Receiver apparatus as set forth in claim 12, for usefully receiving vestigial-sideband amplitude-modulated carrier waves transmitting trellis-coded digital information wherein said TRS codewords are all of a standard length in number of bytes therein irrespective of various permissible strengths of said TRS coding, a respective strength of said TRS codewords in each said field of two-dimensionally-coded randomized digital data being signaled by said transmission parameter channel information, said receiver apparatus characterized by said byte-error-location-information register temporarily storing a fixed number of bits equal to the number of bytes in each of said TRS codewords of said standard length.

14. Receiver apparatus as set forth in claim 13, wherein said standard length of all said TRS codewords is 235 bytes.

15. Receiver apparatus as set forth in claim 13, wherein said turbo decoder is connected for usefully decoding SCCC selected from the baseband trellis-coded digital information supplied from said demodulator, which SCCC is transmitted together with periodic sequences of PCCC each encoding 10 bytes of TPC and at least 37 bytes of FIC.

16. Receiver apparatus as set forth in claim 13, wherein said turbo decoder is connected for usefully decoding SCCC selected from the baseband trellis-coded digital information supplied from said demodulator, which SCCC is transmitted together with periodic sequences of PCCC each encoding 10 bytes of TPC and more than 37 bytes of FIC.

17. Receiver apparatus as set forth in claim 16, wherein said turbo decoder is connected for usefully decoding SCCC selected from the baseband trellis-coded digital information supplied from said demodulator, which SCCC is transmitted together with periodic sequences of PCCC each encoding 10 bytes of TPC and 74 bytes of FIC.

18. Receiver apparatus as set forth in claim 12, wherein said turbo decoder is connected for usefully decoding SCCC selected from the baseband trellis-coded digital information supplied from said demodulator, which SCCC is transmitted together with periodic sequences of PCCC each encoding 10 bytes of TPC and more than 37 bytes of FIC.

19. Receiver apparatus as set forth in claim 18, wherein said turbo decoder is connected for usefully decoding SCCC selected from the baseband trellis-coded digital information supplied from said demodulator, which SCCC is transmitted together with periodic sequences of PCCC each encoding 10 bytes of TPC and 74 bytes of FIC.