TAMPER-AWARE VIRTUAL TPM

• US 20100037315A1
• Filed: 09/03/2009
• Published: 02/11/2010
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Original Assignee: Intel Corporation
• Inventors: Ware, Ryan R., Seifert, Jean-Pierre
• Granted Patent: US 8,453,236 B2
• Time in Patent Office: Days
• US Class Current: 726/22
• CPC Class Codes: G06F 21/554 involving event detection and direct action
• CPC Class Codes: G06F 21/57 Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities

Abstract

Methods, software/firmware and apparatus for implementing a tamper-aware virtual trusted platform module (TPM). Under the method, respective threads comprising a virtual TPM thread and a security-patrol threads are executed on a host processor. In one embodiment, the host processor is a multi-threaded processor having multiple logical processors, and the respective threads are executed on different logical processors. While the virtual TPM thread is used to perform various TPM functions, the security-patrol thread monitors for physical attacks on the processor by implementing various numerical calculation loops, wherein an erroneous calculation is indicative of a physical attack. In response to detection of such an attack, various actions can be taken in view of one or more predefined security policies, such as logging the event, shutting down the platform and/or informing a remote management entity.

Claims

1. A method comprising:

executing a virtual trusted platform module (TPM) thread on a processor to facilitate a virtual TPM; and

executing a security-patrol thread on the processor to detect a physical attack on the processor.

2. The method of claim 1, wherein the processor is a multi-threaded processor having multiple logical processors, and the virtual TPM thread is executed on a first logical processor while the security-patrol thread is executed on a second logical processor.

3. The method of claim 1, wherein the security-patrol thread is embodied as a firmware component.

4. The method of claim 1, wherein the security-patrol thread is embodied as an operating system kernel component.

5. The method of claim 1, wherein the security-patrol thread is embodied as an operating system user application.

6. The method of claim 1, wherein the security-patrol thread detects a physical attack on the processor by performing operations including:

performing a numerical calculation loop; and

monitoring for errors in results calculated by the numerical calculation loop, an error identifying the presence of a physical attack on the processor.

7. The method of claim 6, wherein the numerical calculation loop is designed to employ various logical blocks and elements of the processor to detect a physical attack implemented on portions of the processor proximate to those logical blocks and elements.

8. The method of claim 1 further comprising:

detecting a physical attack on the processor; and

providing information corresponding to detection of the physical attack to a remote management entity.

9. The method of claim 8, wherein the information is provided to the remote management entity using an out-of-band communication channel.

10. The method of claim 8, wherein the information is provided to the remote management entity using an in-band communication channel.

11. The method of claim 1, further comprising:

detecting a physical attack via the security-patrol thread; and

implementing a predefined security policy to be performed in response to a physical attack.

12. The method of claim 11, further comprising:

determining a type of physical attack; and

implementing a predefined security policy in view of the type of physical attack that is determined.

13. A machine-readable storage medium containing instructions that, when executed, cause a processor to perform the method, the method including:

executing a virtual trusted platform module (TPM) thread, to effect virtual TPM functionality; and

executing a security-patrol thread, to detect a physical attack on the processor.

14. The machine-readable storage medium of claim 13, wherein the security-patrol thread is embodied as a firmware component.

15. The machine-readable storage medium of claim 13, wherein the security-patrol thread is embodied as an operating system kernel component.

16. The machine-readable storage medium of claim 13, wherein the security-patrol thread is embodied as an operating system user application.

17. The machine-readable storage medium of claim 13, wherein execution of the security-patrol thread detects a physical attack on the processor by performing operations including:

performing a numerical calculation loop; and

monitoring for errors in results calculated by the numerical calculation loop, an error identifying the presence of a physical attack on the processor.

18. The machine-readable storage medium of claim 17, wherein the numerical calculation loop is designed to employ various logical blocks and elements of the processor to detect the physical attack implemented on portions of the processor proximate to those logical blocks and elements.

19. A computer system, comprising:

a multi-threaded processor;

a memory, operatively-coupled with the multi-threaded processor; and

at least one storage device, operatively-coupled with the multi-threaded processor, to store instructions to execute on the multi-threaded processor, the instructions including;

a virtual trusted platform module (TPM) thread, to effect virtual TPM functionality; and

a security-patrol thread, to detect a physical attack on the processor.

20. The computer system of claim 19, wherein the security-patrol thread comprises a firmware component.

21. The computer system of claim 20, further comprising:

a communications component operatively-coupled with the multi-threaded processor, the communication component having an embedded processor to execute instructions either stored on-board the communication component or in the at least one storage device to facilitate an out-of-band (OOB) communications channel.

22. The computer system of claim 20, further comprising:

instructions embodied as a management agent stored in the at least one storage device, wherein execution of the security-patrol thread and the management agent performs operations including;

detecting a physical attack on the multi-threaded processor; and

employing the OOB communication channel to inform a remote management entity that the physical attack on the processor has been detected.

23. The computer system of claim 20, wherein execution of the security-patrol thread detects the physical attack on the processor by performing operations including:

performing a numerical calculation loop; and

monitoring for errors in results calculated by the numerical calculation loop, an error identifying the presence of the physical attack on the processor.