THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME

• US 20100038642A1
• Filed: 03/17/2009
• Published: 02/18/2010
• Est. Priority Date: 08/18/2008
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Koo, Dong-Seong, Yoo, In-Kyung, Ahn, Hyun-Jae, Yoo, Hun, CHOI, Myoung-Wook, Jang, Jae-Hyuk, Ahn, Ki-Wan
• Application Number:
  US12/405,619
• Publication Number:
  US 20100038642A1
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

A thin film transistor (TFT) array panel includes a substrate, a first signal line disposed on the substrate, a first insulating layer disposed on the first signal line, a second signal line disposed on the first insulating layer, a second insulating layer disposed on the second signal line, the second insulating layer comprising an organic layer, a connection bridge disposed on the second insulating layer, the connection bridge connecting the first signal line with the second signal line, an overcoat disposed on the connection bridge, a first contact hole formed in the first and second insulating layers, the first contact hole exposing a portion of the first signal line, and a second contact hole formed in the second insulating layer, the second contact hole exposing a portion of the second signal line, wherein the connection bridge connects the first and second signal lines through the first and second contact holes.

Claims

1. A thin film transistor (TFT) array panel comprising:

a substrate;

a first signal line disposed on the substrate;

a first insulating layer disposed on the first signal line;

a second signal line disposed on the first insulating layer;

a second insulating layer disposed on the second signal line, the second insulating layer comprising an organic layer;

a connection bridge disposed on the second insulating layer, the connection bridge connecting the first signal line with the second signal line;

an overcoat disposed on the connection bridge;

a first contact hole formed in the first and second insulating layers, the first contact hole exposing a portion of the first signal line; and

a second contact hole formed in the second insulating layer, the second contact hole exposing a portion of the second signal line,

wherein the connection bridge connects the first and second signal lines through the first and second contact holes.

2. The TFT array panel of claim 1, wherein the overcoat comprises an inorganic material.

3. The TFT array panel of claim 2, wherein the inorganic material comprises at least one of silicon oxide and silicon nitride.

4. The TFT array panel of claim 1, wherein the second insulating layer further comprises an inorganic layer disposed under the organic layer.

5. The TFT array panel of claim 4, wherein a thickness of the organic layer is greater than about 2 μ

m.

6. The TFT array panel of claim 1, wherein the connection bridge comprises at least one of Indium Tin Oxide (ITO) and Indium Zinc Oxide (IZO).

7. The TFT array panel of claim 1, wherein the first and second signal lines transmit a common voltage.

8. The TFT array panel of claim 1, further comprising:

a gate line transmitting a gate signal, the gate line comprising a gate pad;

a data line insulatively crossing the gate line and transmitting a data voltage, the data line comprising a data pad;

a TFT connected to the gate line and the data line;

a pixel electrode connected to the TFT, the pixel electrode receiving the data voltage from the TFT;

a first contact assistant connected to the gate pad; and

a second contact assistant connected to the data pad,

wherein the pixel electrode and the first and second contact assistants are disposed in a same layer as the connection bridge.

9. The TFT array panel of claim 1, wherein the overcoat has substantially the same planar shape as the connection bridge.

10. A method of manufacturing a thin film transistor (TFT) array panel, comprising:

forming a first signal line on a substrate;

forming a first insulating layer on the first signal line;

forming a second signal line on the first insulating layer;

forming a second insulating layer comprising an organic layer on the second signal line;

forming a first contact hole in the first and second insulating layers, the first contact hole exposing a portion of the first signal line;

forming a second contact hole in the second insulating layer, the second contact hole exposing a portion of the second signal line;

forming a connection bridge on the second insulating layer using a first photomask, the connection bridge connecting the first and second signal lines through the first and second contact holes; and

forming an overcoat on the connection bridge using the first photomask.

11. The method of claim 10, wherein forming the connection bridge and forming the overcoat comprises:

depositing a transparent conductive layer and an inorganic insulating layer on the second insulating layer;

coating a photosensitive film on the inorganic insulating layer;

exposing the photosensitive film to light using the first photomask to form a first photosensitive film pattern comprising a first portion and a second portion, the second portion being thinner than the first portion;

etching the inorganic insulating layer using the first photosensitive film pattern as an etching mask to form an intermediate inorganic insulating layer;

removing the second portion of the first photosensitive film pattern to form a second photosensitive film pattern;

etching the transparent conductive layer using the second photosensitive film pattern and the intermediate inorganic insulating layer as an etching mask;

etching the intermediate inorganic insulating layer to remove the intermediate inorganic insulating layer not covered by the second photosensitive film pattern; and

removing the second photosensitive film pattern.

12. The method of claim 11, wherein the first photomask comprises a transparent part transmitting light, an opaque part blocking light, and a translucent part partially transmitting light.

13. The method of claim 12, wherein the translucent part comprises at least one of a slit pattern, a lattice pattern, and a translucent film.

14. The method of claim 10, wherein forming the first signal line comprises forming a gate line comprising a gate pad, forming the second signal line comprising forming a data line having a data pad and a drain electrode on the first insulating layer, forming a semiconductor on the data line and the drain electrode, and forming an ohmic contact on the semiconductor, and forming the connection bridge and the overcoat comprises forming a pixel electrode connected to the drain electrode, a first contact assistant connected to the gate pad, and a second contact assistant connected to the data pad.

15. The method of claim 14, wherein forming the data line, the drain electrode, the semiconductor, and the ohmic contact together with the second signal line comprises using a second photomask.

16. The method of claim 15, wherein the second photomask comprises a transparent part transmitting light, an opaque part blocking light, and a translucent part partially transmitting light.

17. The method of claim 15, wherein the ohmic contact, the second signal line, the data line, and the drain electrode have substantially the same planar shape.

18. The method of claim 10, wherein the overcoat comprises an inorganic material.

19. The method of claim 18, wherein the inorganic material comprises at least one of silicon oxide and silicon nitride.

20. The method of claim 10, wherein forming the second insulating layer further comprises depositing an inorganic layer before coating of the organic layer.

21. The method of claim 20, wherein a thickness of the organic layer is greater than about 2 μ

m.

22. The method of claim 10, wherein forming the connection bridge comprises depositing Indium Tin Oxide (ITO) and Indium Zinc Oxide (IZO).