INTEGRATING FABRICATION OF PHOTODETECTOR WITH FABRICATION OF CMOS DEVICE ON A SILICON-ON-INSULATOR SUBSTRATE

• US 20100038689A1
• Filed: 08/13/2008
• Published: 02/18/2010
• Est. Priority Date: 08/13/2008
• Status: Abandoned Application

• Current Assignee: Board of Regents of the University of Texas System (University of Texas System)
• Original Assignee: Board of Regents of the University of Texas System (University of Texas System)
• Inventors: Ahn, Donghwan, Campbell, Joe C., Banerjee, Sanjay
• Application Number:
  US12/191,189
• Publication Number:
  US 20100038689A1
• Time in Patent Office: Days
• US Class Current: 257/292
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 31/02019 for devices characterised by at least one potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/028 including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/0304 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 31/0352 characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
• CPC Class Codes: H01L 31/035281 Shape of the body
• CPC Class Codes: H01L 31/105 the potential barrier being of the PIN type
• CPC Class Codes: H01L 31/1808 including only Ge
• CPC Class Codes: H01L 31/184 the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

A method and semiconductor device for integrating the fabrication of a photodetector with the fabrication of a CMOS device on a SOI substrate. The SOI substrate is divided into two regions, a CMOS region and an optical detecting region. After the CMOS device is fabricated in the CMOS region, the optical detecting region is patterned and etched through the top silicon layer and the buried oxide layer to the base silicon layer. The pattern is etched to a depth so that after a material of a photodetector is deposited in the etched pattern, the material grows to the surface level of the SOI substrate. After the formation of a photodetector structure in the optical detecting region, the metallization process is performed on the CMOS device and the photodetector. In this manner, the fabrication of a photodetector is integrated with the fabrication of a CMOS device on the SOI substrate.

Claims

1. A method for integrating the fabrication of a photodetector with the fabrication of a Complementary Metal-Oxide-Semiconductor (“

CMOS”

) device on a Silicon-On-Insulator (“

SOI”

) substrate, the method comprising;

fabricating said CMOS device on said SOI substrate, wherein said SOI substrate comprises a stacking structure of a base silicon layer, a buried oxide layer, and a top silicon layer;

placing a protective dielectric layer over said CMOS device after said fabrication of said CMOS device and prior to a metallization process step;

patterning and etching through said top silicon layer and said buried oxide layer to said base silicon layer in an optical detecting region of said SOI substrate, wherein said pattern is etched to a depth so that after a material of a photodetector is deposited in said etched pattern, said material grows to a surface level of said SOI substrate;

depositing a buffer layer in said etched pattern;

depositing an epitaxial layer of said material of said photodetector on said buffer layer in said etched pattern;

growing said deposited epitaxial layer of said material of said photodetector in said etched pattern in such a manner as to allow said material to grow to said surface level of said SOI substrate; and

performing said metallization on said CMOS device and said photodetector.

4. The method as recited in claim 1 further comprising:

forming a metal-semiconductor-metal photodetector structure in said optical detecting region after said deposited epitaxial layer of said material of said photodetector is grown to said surface level of said SOI substrate.

5. The method as recited in claim 1, wherein said material of said photodetector comprises germanium.

6. The method as recited in claim 1, wherein said material of said photodetector comprises III-V compound semiconductor material.

7. The method as recited in claim 1, wherein said material of said photodetector is compatible with silicon.

8. The method as recited in claim 1, wherein said pattern is etched to a barrier of said buried oxide layer and said base silicon layer.

9. The method as recited in claim 1, wherein said pattern is over-etched into a portion of said base silicon layer.

2. The method as recited 1 further comprising:

forming a p-i-n photodetector structure in said optical detecting region after said deposited epitaxial layer of said material of said photodetector is grown to said surface level of said SOI substrate.

3. The method as recited 1 further comprising:

forming an n-i-p photodetector structure in said optical detecting region after said deposited epitaxial layer of said material of said photodetector is grown to said surface level of said SOI substrate.

10. A semiconductor device, comprising:

a CMOS region fabricated on a Silicon-On-Insulator (“

SOI”

) substrate, wherein said SOI substrate comprises a stacking structure of a base silicon layer, a buried oxide layer, and a top silicon layer, wherein said CMOS region comprises;

a p-type Metal-Oxide-Semiconductor Field-Effect Transistor (“

MOSFET”

); and

an n-type MOSFET; and

an optical detecting region fabricated on said SOI substrate, wherein said optical detecting region comprises a photodetector, wherein an epitaxial layer of material of said photodetector is grown from a buffer layer deposited on said base silicon layer to a substrate surface level of said SOI substrate, wherein a top surface of said photodetector is level with said substrate surface level.

11. The semiconductor device as recited in claim 10, wherein said photodetector comprises a p-i-n photodetector structure.

12. The semiconductor device as recited in claim 10, wherein said photodetector comprises an n-i-p photodetector structure.

13. The semiconductor device as recited in claim 10, wherein said photodetector comprises a metal-semiconductor-metal photodetector structure.

14. The semiconductor device as recited in claim 10, wherein said material of said photodetector comprises germanium.

15. The semiconductor device as recited in claim 10, wherein said material of said photodetector comprises III-V compound semiconductor material.

16. The semiconductor device as recited in claim 10, wherein said material of said photodetector is compatible with silicon.

17. The semiconductor device as recited in claim 10, wherein said epitaxial layer of material of said photodetector is grown from said buffer layer located at a barrier of said buried oxide layer and said base silicon layer.

18. The semiconductor device as recited in claim 10, wherein said epitaxial layer of material of said photodetector is grown from said buffer layer located within a portion of said base silicon layer.