Vertical power MOSFET semiconductor apparatus having separate base regions and manufacturing method thereof

• US 20100038710A1
• Filed: 09/14/2009
• Published: 02/18/2010
• Est. Priority Date: 08/26/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Ohtani, Kinaya, Kobayashi, Kenya
• Granted Patent: US 8,314,460 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor apparatus according to the present invention includes a first semiconductor layer of a first conductive type, a low concentration base region of a second conductive type formed on the first semiconductor layer, a gate electrode formed in a trench with insulating film on an inner surface of the trench that is formed to reach the first semiconductor layer from a surface of the low concentration base region, a source region of the first conductive type formed, contacting the insulating film, on a surface of the low concentration base region, a first high concentration base region, a second high concentration base region provided below and separated from the first concentration base region, and a third high concentration base region of the second conductive type included inside the low concentration base region, provided below and separated from the second high concentration base region.

Claims

1. A semiconductor apparatus,

comprising:

a first semiconductor layer of a first conductive type;

a low concentration base region of a second conductive type formed on the first semiconductor layer;

a gate electrode formed in a trench with an insulating film formed on an inner surface of the trench that is formed to reach the first semiconductor layer from a surface of the low concentration base region;

a source region of the first conductive type formed contacting the insulating film on a surface of the low concentration base region;

a first high concentration base region of the second conductive type formed on the surface of the low concentration base region;

a second high concentration base region of the second conductive type formed to be included inside the low concentration base region, provided below and separated from the first high concentration base region; and

a third high concentration base region of the second conductive type configured to be included inside the low concentration base region, provided below and separated from the second high concentration base region.

2. The semiconductor apparatus according to claim 1, wherein the first high concentration base region is configured to contact a junction between the low concentration base region and the first semiconductor layer.

3. The semiconductor apparatus according to claim 1, wherein the second high concentration base region is formed separate from a junction between the low concentration base region and the first semiconductor layer.

4. The semiconductor apparatus according to claim 1, wherein a width of the first high concentration base region is approximately the same as a width of the second high concentration base region, and a part of the second high concentration base region is formed straight below the first high concentration base region.

5. The semiconductor apparatus according to claim 2, wherein a width of the first high concentration base region is approximately the same as a width of the second high concentration base region, and a part of the second high concentration base region is formed straight below the first high concentration base region.

6. The semiconductor apparatus according to claim 3, wherein a width of the first high concentration base region is approximately the same as a width of the second high concentration base region, and a part of the second high concentration base region is formed straight below the first high concentration base region.

7. The semiconductor apparatus according to claim 1, wherein a width of the first high concentration base region is different from a width of the second high concentration base region, and a part of the second high concentration base region is formed straight below the first high concentration base region.

8. The semiconductor apparatus according to claim 2, wherein a width of the first high concentration base region is different from a width of the second high concentration base region, and a part of the second high concentration base region is formed straight below the first high concentration base region.

9. The semiconductor apparatus according to claim 3, wherein a width of the first high concentration base region is different a width of the second high concentration base region, and a part of the second high concentration base region is formed straight below the first high concentration base region.

10. The semiconductor apparatus according to claim 1, wherein the third high concentration base region is formed between the first high concentration base region and the second high concentration base region.

11. The semiconductor apparatus according to claim 1, wherein the first semiconductor layer comprises:

a semiconductor substrate of the first conductive type; and

an epitaxial layer of the first conductive type formed on the semiconductor substrate,

wherein the trench is formed to reach the epitaxial layer.

12. A method of manufacturing a semiconductor apparatus, the method comprising:

forming a trench on a surface of a first semiconductor layer of a first conductive type;

forming a gate electrode in the trench with an insulating film on an inner surface of the trench;

forming a low concentration base region of a second conductive type on the surface of the first semiconductor layer;

forming a source region of the first conductive type on a surface of the low concentration base region;

forming a first high concentration base region of the second conductive type on the surface of the low concentration base region;

forming a second high concentration base region of the second conductive type to be included in the low concentration base region, provided below and separated from the first high concentration base region; and

forming a third high concentration base region of the second conductive type configured to be included inside the low concentration base region, provided below and separated from the second high concentration base region.

13. The method of manufacturing the semiconductor apparatus according to claim 12, wherein the second high concentration base region is formed by implanting ions into the low concentration base region with a higher energy than an energy for the first high concentration base region.

14. A semiconductor apparatus, comprising:

a drain electrode;

a first semiconductor layer of a first conductive type formed on the drain electrode;

an epitaxial layer of the first conductive type formed on the first semiconductor layer;

a low concentration base region of a second conductive type formed on the epitaxial layer;

a gate electrode formed in a trench;

a first high concentration base region of the second conductive type formed on the surface of the low concentration base region;

a second high concentration base region of the second conductive type included inside the low concentration base region, provided below and separate from the first high concentration base; and

a third high concentration base region of the second conductive type configured to be included inside the low concentration base region, provided below and separate from the second high concentration base region and above and separate from the epitaxial layer.

15. The semiconductor apparatus of claim 14, wherein the gate electrode comprises an insulating film formed on an inner surface of the trench that is formed to reach the first semiconductor layer from a surface of the low concentration base region.

16. The semiconductor apparatus of claim 15, further comprising an interlayer dielectric, the interlayer dielectric being provided on a top surface of the gate electrode.

17. The semiconductor apparatus of claim 16, wherein the interlayer dielectric is provided on a top surface of the insulating film.

18. The semiconductor apparatus of claim 14, wherein the second high concentration base region is closer to the first high concentration base region than a bottom surface of the trench and is shallower than the depth of a bottom surface of the trench.

19. The semiconductor apparatus of claim 14, wherein the first high concentration base region of the second conductive type is provided above a top surface of the epitaxial layer.

20. The semiconductor apparatus of claim 14, further comprising a source region of the first conductive type formed, contacting the insulating film, on a surface of the low concentration base region.