INFORMATION STORAGE SYSTEM WHICH INCLUDES A BONDED SEMICONDUCTOR STRUCTURE

• US 20100038743A1
• Filed: 10/19/2009
• Published: 02/18/2010
• Est. Priority Date: 06/24/2003
• Status: Active Grant

• Current Assignee: BeSang Inc.
• Original Assignee: BeSang Inc.
• Inventors: Lee, Sang-Yun
• Granted Patent: US 8,471,263 B2
• Time in Patent Office: Days
• US Class Current: 257/499
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 53/20 characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type

Abstract

An information storage system includes a bonded semiconductor structure having a memory circuit region carried by an interconnect region. The memory circuit region includes a memory control device region having a vertically oriented memory control device. The memory circuit region includes a memory device region in communication with the memory control device region. The memory device region includes a memory device whose operation is controlled by the vertically oriented memory control device.

Claims

1. A bonded semiconductor structure, comprising:

a vertically oriented semiconductor device carried by a conductive bonding contact region which establishes a bonding interface; and

a memory device region in communication with the vertically oriented semiconductor device;

wherein the memory device region is responsive to a signal which flows through the bonding interface.

2. The structure of claim 1, wherein the signal flows through the vertically oriented semiconductor device.

3. The structure of claim 1, wherein the vertically oriented semiconductor device includes a stack of semiconductor regions.

4. The structure of claim 3, wherein the stack extends between the bonding interface and memory device region.

5. The structure of claim 1, wherein the memory device region includes a ferroelectric memory device.

6. The structure of claim 1, wherein the memory device region includes a phase change memory device.

7. The structure of claim 1, wherein the memory device region includes a magnetoresistive memory device.

8. A bonded semiconductor structure, comprising:

a vertically oriented semiconductor device in communication with an interconnect region through a bonding interface, wherein the vertically oriented semiconductor device includes a mesa structure;

a memory device region in communication with the vertically oriented semiconductor device; and

a conductive bonding contact region which carries the mesa structure.

9. The structure of claim 8, wherein the mesa structure includes a planarized surface which faces the bonding interface.

10. The structure of claim 8, wherein the memory device region is responsive to a signal which flows through the bonding interface and conductive bonding contact region.

11. The structure of claim 8, further including a control dielectric which extends around a sidewall of the mesa structure.

12. The structure of claim 11, further including a control terminal operatively coupled with the mesa structure through the control dielectric.

13. The structure of claim 8, wherein the mesa structure extends between the conductive bonding contact region and memory device region.

14. An information storage system, comprising:

a controller circuit;

an interconnect region carried by the controller circuit; and

a memory circuit region carried by the interconnect region, the memory circuit including a vertically oriented semiconductor device in communication with the controller circuit through a bonding interface.

15. The system of claim 14, wherein the memory device region includes a ferroelectric memory device in communication with the vertically oriented semiconductor device through a via.

16. The system of claim 14, wherein the memory device region includes a phase change memory device in communication with the vertically oriented semiconductor device through a via.

17. The system of claim 14, wherein the memory device region includes a magnetoresistive memory device in communication with the vertically oriented semiconductor device through a via.

18. The system of claim 14, wherein the memory device region includes a capacitor in communication with the vertically oriented semiconductor device through a via.

19. The system of claim 14, wherein the vertically oriented semiconductor device includes a mesa structure with a planarized surface which faces the interconnect region.

20. The system of claim 19, wherein the mesa structure includes a sidewall which extends away from the bonding interface and controller circuit.

21. The system of claim 14, wherein the memory circuit region is responsive to a signal which flows through the bonding interface.

22. The system of claim 14, wherein the controller circuit provides a signal in response to an indication from the Internet, the memory circuit region being responsive to the signal.

23. The system of claim 14, wherein the controller circuit provides the signal in response to an indication from a computer network, the memory circuit region being responsive to the signal.

24. The system of claim 14, wherein the controller circuit provides the signal in response to an indication from a processor, the memory circuit region being responsive to the signal.