METHOD, CIRCUIT, AND DESIGN STRUCTURE FOR CAPTURING DATA ACROSS A PSEUDO-SYNCHRONOUS INTERFACE

• US 20100039150A1
• Filed: 08/15/2008
• Published: 02/18/2010
• Est. Priority Date: 08/15/2008
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: Kuemerle, Mark W., Hanudel, Christopher D., Berhanu, Malede W., Ogilvie, Clarence R., Milton, David W., Smith, Jack R.
• Granted Patent: US 8,189,723 B2
• Time in Patent Office: Days
• US Class Current: 327/153
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04L 7/0037 Delay of clock signal

Abstract

A method for source synchronous communication. The method includes dynamically adjusting a delay that is applied to a data signal and a remote clock signal until a delayed remote clock signal is synchronized with a local clock signal, and capturing data from a delayed data signal associated with the delay in a local domain.

Claims

1. A method for source synchronous communication, comprising:

dynamically adjusting a delay that is applied to a data signal and a remote clock signal until a delayed remote clock signal is synchronized with a local clock signal; and

capturing data from a delayed data signal associated with the delay in a local domain.

2. The method of claim 1, wherein the delay time shifts the data signal by a first amount to generate the delayed data signal, and

the delay time shifts the remote clock signal by the first amount to generate the delayed remote clock signal.

3. The method of claim 1, further comprising generating the data signal and the remote clock signal at a first location on a chip.

4. The method of claim 3, wherein the local domain is at a second location of the chip.

5. The method of claim 3, wherein the data signal is aligned with the remote clock signal.

6. The method of claim 1, wherein the dynamically adjusting is based on a value held in a delay register and at least one value of a state of the delayed remote clock signal.

7. The method of claim 6, further comprising capturing the at least one value of the state of the delayed remote clock signal when the local clock signal goes from a low state to a high state.

8. The method of claim 7, further comprising one of:

synchronizing a falling edge of the delayed remote clock signal with a rising edge of the local clock signal, and

synchronizing a rising edge of the delayed remote clock signal with a falling edge of the local clock signal.

9. A method for on-chip source synchronous communication, comprising:

providing a circuit comprising hardware structured and arranged to;

apply a delay to a data signal and a remote clock signal aligned with the data signal, wherein the delay is based upon a value held in a delay register;

change the value in the delay register based upon at least one captured state of a delayed remote clock signal, wherein the at least one captured state of the delayed remote clock signal is captured upon a change of state of a local clock signal; and

repeat the applying and the changing at least until the delayed remote clock signal is aligned with the local clock signal.

10. The method of claim 9, wherein the circuit is provided in a source synchronous communication path of a chip.

11. The method of claim 9, wherein the at least one captured state of the delayed remote clock signal is a single captured state having a value of one of zero and one.

12. The method of claim 11, wherein:

when the single captured state is zero, the circuit is further arranged to change the value in the delay register by adding a predefined adjustment unit, and

when the single captured state is one, the circuit is further arranged to change the value in the delay register by subtracting the predefined adjustment unit.

13. The method of claim 9, wherein the at least one captured state of the delayed remote clock signal comprises a first captured state and a second captured state, each having a value of one of zero and one.

14. The method of claim 13, wherein:

when the first captured state is zero and the second captured state is zero, the circuit is further arranged to change the value in the delay register by adding a predefined adjustment unit,

when the first captured state is one and the second captured state is zero, the circuit is further arranged to change the value in the delay register by subtracting the predefined adjustment unit,

when the first captured state is zero and the second captured state is one, the circuit is further arranged to not change the value in the delay register, and

when the first captured state is one and the second captured state is one, the circuit is further arranged to change the value in the delay register by subtracting the predefined adjustment unit.

15. The method of claim 9, wherein the circuit repeats the applying and the changing after the delayed remote clock signal is aligned with the local clock signal.

16. The method of claim 9, wherein:

the data signal and the remote clock signal are generated at a first location on a chip, and

the local clock signal is generated by a local clock associated with a local domain that receives the data signal after the data signal has been delayed.

17. A method for on-chip communication, comprising:

receiving a data signal and a remote clock signal associated with the data signal; and

applying a dynamically determined delay to both the data signal and the remote clock signal to create a delayed data signal and a delayed remote clock signal,

wherein the delayed remote clock signal is synchronized with a local clock associated with a local domain that receives the delayed data signal.

18. The method of claim 17, wherein the receiving and the applying are performed by a circuit arranged within a source synchronous communication path on a chip.

19. The method of claim 18, wherein the circuit comprises a state machine that iteratively adjusts the dynamically determined delay based upon at least one value of a state of the delayed remote clock signal, and

20. The method of claim 19, wherein the at least one value of the state of the delayed remote clock signal is captured upon a change of state of the local clock signal.