NOVEL METHOD TO INTEGRATE GATE ETCHING AS ALL-IN-ONE PROCESS FOR HIGH K METAL GATE

• US 20100041236A1
• Filed: 02/06/2009
• Published: 02/18/2010
• Est. Priority Date: 08/18/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Yih-Ann, Lin, Jr Jung, Chen, Ryan Chia-Jen
• Granted Patent: US 8,304,349 B2
• Time in Patent Office: Days
• US Class Current: 438/704
• CPC Class Codes: H01L 21/02071 the processing being a delineation, e.g. RIE, of conductive layers
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes applying a first dry etching process to a semiconductor substrate in an etch chamber through openings of a patterned mask layer defining gate regions, removing a polysilicon layer and a metal gate layer on the semiconductor substrate; applying a H2O steam to the semiconductor substrate in the etch chamber, removing a capping layer on the semiconductor substrate; applying a second dry etching process to the semiconductor substrate in the etch chamber, removing a high k dielectric material layer; and applying a wet etching process to the semiconductor substrate to remove polymeric residue.

Claims

1. A method for making metal gate stacks of a semiconductor device comprising:

applying a first dry etching process to a semiconductor substrate in an etch chamber through openings of a patterned mask layer defining gate regions, removing a polysilicon layer and a metal gate layer on the semiconductor substrate;

applying a H2O steam to the semiconductor substrate in the etch chamber, removing a capping layer on the semiconductor substrate; and

applying a second dry etching process to the semiconductor substrate in the etch chamber, removing a high k dielectric material layer.

2. The method of claim 1, further comprising applying a wet etching process to the semiconductor substrate to remove a polymeric residue after applying the second dry etching process.

3. The method of claim 1, wherein the capping layer comprises Lanthanum (La) oxide.

4. The method of claim 1, wherein applying the H2O steam comprises implementing H2O to the capping layer with an etch rate greater than about 30 angstrom per minute.

5. The method of claim 1, wherein the semiconductor device is an N-type metal-oxide-semiconductor field-effect-transistor (NMOSFET).

6. The method of claim 1, wherein the metal gate layer comprises titanium nitride.

7. The method of claim 1, wherein the metal gate layer comprises a conductive material selected from the group consisting of tantalum nitride, molybdenum nitride, and titanium aluminum nitride.

8. The method of claim 1, wherein applying the H2O steam comprises providing the semiconductor substrate to a temperature higher than about 100 degree C.

9. The method of claim 1, wherein the patterned hard mask comprises silicon nitride.

10. A method for making metal gate stacks of a semiconductor device comprising:

applying a first dry etching process to a semiconductor substrate in an etch chamber through openings of a patterned mask layer defining gate regions, removing a gate metal layer on the semiconductor substrate;

applying at least one of an oxygen plasma and argon plasma to the semiconductor substrate in the etch chamber, removing a capping layer;

applying a second dry etching process to the semiconductor substrate in the etch chamber, removing a high k dielectric material layer; and

applying a wet etching process to the semiconductor substrate to remove a polymeric residue.

11. The method of claim 10, wherein the capping layer comprises lanthanum oxide (LaO).

12. The method of claim 10, wherein the metal gate layer comprises a conductive material selected from the group consisting of titanium nitride, tantalum nitride, molybdenum nitride, and titanium aluminum nitride.

13. The method of claim 10, wherein applying the first dry etching process comprises applying the first dry etching process to further remove a polysilicon layer on the metal gate layer.

14. A method for making a semiconductor device comprising:

applying a first dry etching process to a semiconductor substrate in an etch chamber to remove a metal gate layer;

applying at least one of an H2O steam, oxygen plasma, and argon plasma to the semiconductor substrate in the etch chamber to remove a capping layer; and

applying a second dry etching process to the semiconductor substrate in the etch chamber to remove a high k dielectric material layer thereby forming a gate stack.

15. The method of claim 14, further comprising, before applying the first dry etching process, patterning a mask layer on the metal gate layer to define a gate region.

16. The method of claim 14, further comprising applying a wet etching process to the semiconductor substrate in a wet etch tool to remove a polymeric residue after the second dry etch process.

17. The method of claim 14, wherein the capping layer comprises La oxide.

18. The method of claim 14, wherein applying the first dry etching process comprises applying the first dry etching process to a polysilicon layer on the metal gate layer.

19. The method of claim 14, wherein the gate stack is a gate structure of an N-type metal-oxide-semiconductor field-effect-transistor (NMOSFET).

20. The method of claim 14, wherein the metal gate layer comprises titanium nitride.