SNOOP-BASED PREFETCHING

• US 20100042786A1
• Filed: 08/14/2008
• Published: 02/18/2010
• Est. Priority Date: 08/14/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: BELL, Gordon Bernard, DERBY, Jeffrey Haskell, VU, Ken, RAMANI, Srinivasan, KRISHNA, Anil, DAVIS, Gordon Taylor, WOOLET, Steve
• Granted Patent: US 8,200,905 B2
• Time in Patent Office: Days
• US Class Current: 711/121
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/6026 Prefetching based on access pattern detection, e.g. stride based prefetch

Abstract

A processing system is disclosed. The processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.

Claims

1. A processing system comprising:

a memory;

a first core configured to process applications;

wherein the first core includes a first cache;

a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and

a second core configured to process at least one software algorithm;

wherein the at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses;

wherein the second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and wherein the prefetched data is provided to the first core if requested.

2. The processing system of claim 1 wherein the at least one software algorithm targets prefetching data that is required by the first core.

3. The processing system of claim 1 wherein the prefetched data is stored in a second cache that is accessible by the first core.

4. The processing system of claim 1 wherein the second core is underutilized.

5. The processing system of claim 3 wherein the second cache is shared by the first core and the second core.

6. The processing of claim 3 wherein the second cache is a private cache accessible by the first core.

7. The processing system of claim 1 wherein the sequence of addresses trigger a miss request which is visible on a shared interconnect between the first core and the second core.

8. The processing system of claim 1 wherein the prefetched data is provided to the application based on a demand fetch.

9. The processing system of claim 8 wherein the demand fetch is provided via data intervention via a shared interconnect.

10. The processing system of claim 8 wherein the demand fetch is provided via data intervention via a shared cache level.

11. A system comprising:

at least one software prefetch algorithm configured to be executed on a first processor core of a central processing system; and

a hardware support mechanism which interacts with the software algorithm to filter prefetch addresses associated with a second processor core running a main application and for retrieving the appropriate prefetch addresses.

12. The system of claim 11 wherein the hardware support mechanism comprises:

an input queue for receiving snooped demand fetch addresses from the main application;

an output queue for receiving appropriate prefetch addresses based upon the software prefetch algorithm; and

a DMA engine for obtaining the appropriate prefetch data corresponding to addresses from the output queue and placing the data into the cache associated with the processor core.

13. The system of claim 11 wherein the at least one software algorithm comprises a library of prefetch software algorithms.

14. The system of claim 11 wherein the first processor core is underutilized.

15. The system of claim 11 wherein the control processing system includes a cache which is accessible by the first and second processor cores.

16. The system of claim 11 wherein the prefetch addresses trigger a miss request which is visible on a shared interconnect between the first processor core and the second processor core.

17. A method comprising:

providing at least one software prefetch algorithm configured to be executed on a first processor core of a central processing system; and

providing a hardware support mechanism which interacts with the software algorithm to filter prefetch addresses associated with a second processor core running a main application and for retrieving the appropriate prefetch addresses.

18. The method of claim 17 wherein the hardware support mechanism comprises:

an input queue for receiving snooped demand fetch addresses from the main application;

an output queue for receiving appropriate prefetch addresses based upon the software prefetch algorithm; and

a DMA engine for obtaining the appropriate prefetch data corresponding to addresses from the output queue and placing the data into the cache associated with the processor core.

19. The method of claim 17 wherein the at least one software algorithm comprises a library of prefetch software algorithms.

20. The method of claim 17 wherein the first processor core is underutilized.

21. The method of claim 17 wherein the control processing system includes a cache which is accessible by the first and second processor cores.

22. The method of claim 17 wherein the prefetch addresses trigger a miss request which is visible on a shared interconnect between the first processor core and the second processor core.