MULTICORE PROCESSOR AND METHOD OF CONTROLLING MULTICORE PROCESSOR

• US 20100042870A1
• Filed: 08/06/2009
• Published: 02/18/2010
• Est. Priority Date: 08/12/2008
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: AMATSUBO, Takanao
• Application Number:
  US12/536,910
• Publication Number:
  US 20100042870A1
• Time in Patent Office: Days
• US Class Current: 714/10
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 15/7871 Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

A multicore processor has a plurality of processor cores each of which is configured to execute a computation, a plurality of reconfigurable devices dynamically reconfigurable in circuit configuration on the basis of circuit information, and a lock state storage section configured to store lock information indicating whether or not each of the reconfigurable devices is locked. The multicore processor also has a plurality of reconfigurable control sections each of which is configured to load circuit information for a computation to be executed into one of the reconfigurable devices not locked, by referring to the lock information, performs execution of the computation with the reconfigurable device and execution of the computation with the one of the processor cores in parallel with each other, and perform control so that results of execution of the computation completed faster are adopted.

Claims

1. A multicore processor comprising:

a plurality of processor cores each of which is configured to execute a computation based on a program;

a plurality of reconfigurable devices each reconfigurable dynamically in circuit configuration on the basis of circuit information;

a lock state storage section configured to store lock information indicating whether or not each of the reconfigurable devices is locked by one of the plurality of processor cores; and

a plurality of reconfigurable control sections respectively provided in correspondence with the plurality of processor cores, each of the reconfigurable control sections configured to execute;

determining whether or not circuit information for a computation to be executed is loaded in each of the reconfigurable devices, and if the circuit information for the computation to be executed is loaded, referring to the lock information and performing only execution of the computation with the reconfigurable device in which the circuit information for the computation to be executed is loaded, without executing the computation to be executed in any of the plurality of processor cores, when the reconfigurable device in which the circuit information for the computation to be executed is loaded is not locked, and if the circuit information for the computation to be executed is not loaded, loading the circuit information for the computation to be executed in one of the reconfigurable devices not locked, by referring to the lock information, performing execution of the computation with the reconfigurable device in which the circuit information for the computation to be executed is loaded and execution of the computation with one of the plurality of processor cores in parallel with each other, and performing control so that results of the execution of the computation completed faster between results of the two executions of the computation performed in parallel with each other are adopted as results of the computation to be executed.

2. The multicore processor according to claim 1, wherein the lock state storage section further stores final execution information indicating whether or not each of the reconfigurable devices is performing processing for a final computation, and

wherein each of the plurality of reconfigurable control sections refers to the final execution information and, if one of the reconfigurable devices is performing processing for the final computation, the reconfigurable control section loads part of the circuit information into the reconfigurable device performing processing for the final computation, loads the rest of the circuit information into the reconfigurable device after the completion of the final computation, and reconfigures the circuit configuration of the reconfigurable device.

3. The multicore processor according to claim 1, wherein each of the plurality of reconfigurable devices has a register configured to hold loaded circuit information, and

wherein each of the plurality of reconfigurable control sections determines, by referring to the register, whether or not the circuit information for the computation to be executed is loaded in each of the reconfigurable devices.

4. The multicore processor according to claim 1, wherein when loading the circuit information, each of the reconfigurable control sections changes the reconfigurable device into which the circuit information is loaded from a low power consumption mode to a normal power consumption mode.

5. The multicore processor according to claim 1, wherein when loading the circuit information for the computation to be executed into the reconfigurable device not locked, each of the plurality of reconfigurable control sections changes the lock information on the reconfigurable device into which the circuit information for the computation to be executed is loaded into lock information indicating that the reconfigurable device is locked by one of the plurality of processor cores.

6. The multicore processor according to claim 1, wherein if all of the reconfigurable devices are locked as a result of reference to the lock information, the computation to be executed is executed in one of the plurality of processor cores.

7. The multicore processor according to claim 1, wherein the lock information includes information formed of an on-loading bit indicating whether or not the circuit information for the computation to be executed is being loaded into each of the reconfigurable devices, and information formed of an on-execution bit indicating whether or not each of the reconfigurable devices is executing the computation to be executed.

8. The multicore processor according to claim 1, further comprising:

a plurality of BIST circuits respectively provided in correspondence with the plurality of reconfigurable devices, each of the BIST circuits configured to perform a self-test on the corresponding reconfigurable device; and

a device state storage section configured to store results of the self-tests performed by the plurality of BIST circuits,

wherein each of the plurality of BIST circuits stores the result of the self-test in the device state storage section, and

wherein if an abnormality exists in the results of the self-tests stored in the device state storage section, one of the plurality of processor cores locks the reconfigurable device having the abnormality.

9. The multicore processor according to claim 8, wherein one of the plurality of processor cores locks the reconfigurable device having the abnormality by changing the lock information on the reconfigurable device having the abnormality into lock information indicating that the reconfigurable device is locked by one of the plurality of processor cores.

10. The multicore processor according to claim 8, wherein one of the plurality of processor cores displays information on the reconfigurable device having the abnormality on a display device.

11. A method of controlling a multicore processor, comprising:

storing lock information indicating whether or not each of a plurality of reconfigurable devices reconfigurable dynamically in circuit configuration on the basis of circuit information is locked by one of a plurality of processor cores each of which is configured to execute a computation based on a program;

determining whether or not circuit information for a computation to be executed is loaded in each of the reconfigurable devices;

if the circuit information for the computation to be executed is loaded, referring to the lock information, and performing only execution of the computation with the reconfigurable device in which the circuit information for the computation to be executed is loaded, without executing the computation to be executed in any of the plurality of processor cores, when the reconfigurable device in which the circuit information for the computation to be executed is loaded is not locked; and

if the circuit information for the computation to be executed is not loaded, loading the circuit information for the computation to be executed in one of the reconfigurable devices not locked, by referring to the lock information, performing execution of the computation with the reconfigurable device in which the circuit information for the computation to be executed is loaded and execution of the computation with one of the plurality of processor cores in parallel with each other, and performing control so that results of the execution of the computation completed faster between results of the two executions of the computation performed in parallel with each other are adopted as results of the computation to be executed.

12. The method of controlling a multicore processor according to claim 11, wherein final execution information indicating whether or not each of the reconfigurable devices is performing processing for a final computation is further stored, and

wherein the final execution information is referred to;

if one of the reconfigurable devices is performing processing for the final computation, part of the circuit information is loaded into the reconfigurable device performing processing for the final computation;

the rest of the circuit information is loaded into the reconfigurable device after the completion of the final computation; and

the circuit configuration of the reconfigurable device is reconfigured.

13. The method of controlling a multicore processor according to claim 11, wherein the loaded circuit information is held, and

wherein determination is made by referring to the circuit information held as to whether or not the circuit information for the computation to be executed is loaded in each of the reconfigurable devices.

14. The method of controlling a multicore processor according to claim 11, wherein when the circuit information is loaded, the reconfigurable device into which the circuit information is loaded is changed from a low power consumption mode to a normal power consumption mode.

15. The method of controlling a multicore processor according to claim 11, wherein the circuit information for the computation to be executed is loaded into the reconfigurable device not locked, the lock information on the reconfigurable device into which the circuit information for the computation to be executed is loaded is changed into lock information indicating that the reconfigurable device is locked by one of the plurality of processor cores.

16. The method of controlling a multicore processor according to claim 11, wherein if all of the reconfigurable devices are locked as a result of reference to the lock information, the computation to be executed is executed in one of the plurality of processor cores.

17. The method of controlling a multicore processor according to claim 11, wherein the lock information includes information formed of an on-loading bit indicating whether or not the circuit information for the computation to be executed is being loaded into each of the reconfigurable devices, and information formed of an on-execution bit indicating whether or not each of the reconfigurable devices is executing the computation to be executed.

18. The method of controlling a multicore processor according to claim 11, wherein a self-test is performed on each of the plurality of reconfigurable devices;

results of the self-test are stored; and

if an abnormality exists in the stored results of the self-test, the reconfigurable device having the abnormality is locked.

19. The method of controlling a multicore processor according to claim 18, wherein the reconfigurable device having the abnormality is locked by changing the lock information on the reconfigurable device having the abnormality into lock information indicating that the reconfigurable device is locked by one of the plurality of processor cores.

20. The method of controlling a multicore processor according to claim 18, wherein information on the reconfigurable device having the abnormality is displayed on a display device.