HYBRID MRAR ARRAY STRUCTURE AND OPERATION
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Accused Products
Abstract
This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.
29 Citations
60 Claims
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1-32. -32. (canceled)
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33. A method of fabricating a magnetic memory device, comprising:
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forming a first sense line; forming a first plurality of magnetic memory bits, each of said first plurality of magnetic memory bits being formed over, and in electrical contact with, said first sense line; forming a second sense line over said first plurality of magnetic memory bits; forming a second plurality of magnetic memory bits, each of said second plurality of memory bits being formed over, and in electrical contact with, said second sense line; and forming an interconnect in electrical contact with said first sense line and said second sense line, wherein said interconnect is in electrical contact with said first plurality of magnetic memory bits via said first sense line, and wherein said interconnect is in electrical contact with said second plurality of magnetic memory bits via said second sense line. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40)
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41. A method of fabricating a phase change memory device, comprising:
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forming a first sense line; forming a first plurality of phase change memory bits, each of said first plurality of phase change memory bits being formed over, and in electrical contact with, said first sense line; forming a second sense line over said first plurality of phase change memory bits; forming a second plurality of phase change memory bits, each of said second plurality of memory bits being formed over, and in electrical contact with, said second sense line; and forming an interconnect in electrical contact with said first sense line and said second sense line, wherein said interconnect is in electrical contact with said first plurality of phase change memory bits via said first sense line, and wherein said interconnect is in electrical contact with said second plurality of phase change memory bits via said second sense line. - View Dependent Claims (42, 43, 44, 45, 46, 47, 48)
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49. A magnetic memory device, comprising:
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a first sense line; a first plurality of magnetic memory bits, each of said first plurality of magnetic memory bits being arranged over, and in electrical contact with, said first sense line; a second sense line arranged over said first plurality of magnetic memory bits; a second plurality of magnetic memory bits, each of said second plurality of memory bits being arranged over, and in electrical contact with, said second sense line; and an interconnect in electrical contact with said first sense line and said second sense line, wherein said interconnect is in electrical contact with said first plurality of magnetic memory bits via said first sense line, and wherein said interconnect is in electrical contact with said second plurality of magnetic memory bits via said second sense line. - View Dependent Claims (50, 51, 52, 53, 54)
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55. A phase change memory device, comprising:
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a first sense line; a first plurality of phase change memory bits, each of said first plurality of phase change memory bits being arranged over, and in electrical contact with, said first sense line; a second sense line arranged over said first plurality of phase change memory bits; a second plurality of phase change memory bits, each of said second plurality of memory bits being arranged over, and in electrical contact with, said second sense line; and an interconnect in electrical contact with said first sense line and said second sense line, wherein said interconnect is in electrical contact with said first plurality of phase change memory bits via said first sense line, and wherein said interconnect is in electrical contact with said second plurality of phase change memory bits via said second sense line. - View Dependent Claims (56, 57, 58, 59, 60)
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Specification