INTEGRATED CIRCUIT METAL GATE STRUCTURE AND METHOD OF FABRICATION

• US 20100044783A1
• Filed: 11/21/2008
• Published: 02/25/2010
• Est. Priority Date: 08/20/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Ming-Yuan, Thei, Kong-Beng, Chuang, Harry, Liang, Mong-Song, Yeh, Chiung-Han
• Granted Patent: US 8,735,235 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method is provided for forming a metal gate using a gate last process. A trench is formed on a substrate. The profile of the trench is modified to provide a first width at the aperture of the trench and a second width at the bottom of the trench. The profile may be formed by including tapered sidewalls. A metal gate may be formed in the trench having a modified profile. Also provided is a semiconductor device including a gate structure having a larger width at the top of the gate than the bottom of the gate.

Claims

1. A method of fabricating a semiconductor device, comprising:

providing a substrate including an insulating layer;

forming a trench in the insulating layer;

modifying the profile of the trench to provide a first width greater than a second width; and

forming a metal gate in the trench having the modifying profile.

2. The method of claim 1, wherein the modifying the profile of the trench includes a sputtering process.

3. The method of claim 1, wherein the modifying the profile of the trench includes a plasma process containing an inert gas.

4. The method of claim 1, wherein the modifying the profile of the trench includes a sputtering process containing argon.

5. The method of claim 1, wherein the sidewalls of the trench include a first portion and a second portion, wherein the first portion is substantially perpendicular the substrate, and the second portion is oblique.

6. The method of claim 1, further comprising:

forming a high-k dielectric layer, wherein the metal gate is formed above the high-k dielectric layer.

7. The method of claim 1, wherein the sidewalls include an upper portion that is oblique to a lower portion, the upper portion being substantially linear.

8. The method of claim 1, wherein the sidewalls include an upper portion that is oblique to a lower portion, the upper portion being curved.

9. The method of claim 1, further comprising:

forming a dummy gate structure on the substrate, wherein the forming the trench includes removing the dummy gate structure to provide an opening forming the trench.

10. The method of claim 1, wherein the forming the trench includes removing dielectric material from the substrate.

11. A semiconductor device, comprising:

a substrate;

a source and a drain region formed on the substrate; and

a gate structure disposed on the substrate between the source and drain regions, the gate structure including;

a gate dielectric layer, wherein the gate dielectric includes a high-k dielectric material; and

a metal gate electrode, wherein the metal gate electrode includes a tapered profile.

12. The device of claim 11, wherein the metal gate electrode includes a curved sidewall.

13. The device of claim 11, wherein the metal gate electrode includes a sidewall oblique to the surface of the substrate.

14. The device of claim 11, wherein the tapered profile includes a tapered angle between approximately 5 and 30 degrees.

15. The device of claim 11, wherein the tapered profile includes a tapered angle between approximately 5 and 20 degrees.

16. A method of semiconductor fabrication, comprising:

providing a semiconductor substrate;

forming a dummy gate structure on the substrate, wherein the dummy gate structure includes polysilicon;

removing the dummy gate structure to provide a trench having a top portion and a bottom portion, wherein the top portion and the bottom portion are of a first width;

increasing the width of the top portion of the trench to provide a second width; and

forming a gate in the trench including the second width, wherein the forming the gate includes depositing a first metal layer into the trench.

17. The method of claim 16, wherein the first metal layer includes nitrogen, carbon, or combination thereof.

18. The method of claim 16, further comprising:

forming a spacer on the substrate adjacent the dummy gate structure, wherein the increasing the width of the top portion of the trench including removing a portion of the spacer.

19. The method of claim 16, wherein the increasing the width of the top portion of the trench includes a sputtering process, a reactive ion etch process, a plasma etch process, or a combination thereof.

20. The method of claim 16, further comprising:

forming a high dielectric constant (high k) gate dielectric layer on the substrate underlying the dummy gate structure.