THREE-DIMENSIONAL STRUCTURAL SEMICONDUCTOR DEVICE

• US 20100044846A1
• Filed: 03/28/2008
• Published: 02/25/2010
• Est. Priority Date: 03/29/2007
• Status: Abandoned Application

• Current Assignee: Foundation for Advancement of International Science, National University Corporation Chiba University
• Original Assignee: National University Corporation Chiba University
• Inventors: Konda, Msahiro, Ohmi, Tadahiro
• Application Number:
  US12/450,441
• Publication Number:
  US 20100044846A1
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device of three-dimensional structure in which the operating frequency of a chip can be raised while preventing the chip area from increasing. The three-dimensional structure semiconductor device have a first integrated circuit including a plurality of areas formed on a first conductor layer and a first wiring layer formed on the first conductor layer, a first insulating layer laminated on the first wiring layer, and a second integrated circuit including a plurality of areas formed on a second conductor layer which is laminated on the first insulating layer, and a second wiring layer formed on the second conductor layer. The first integrated circuit and the second integrated circuit are connected electrically by interconnection penetrating in the laminating direction and at least one of bidirectional communication of data, control signal supply, and clock signal supply between the first integrated circuit and the second integrated circuit is carried out through the penetrating interconnection.

Claims

1. A three-dimensional structural semiconductor device, comprising:

a first integrated circuit constructed so as to include a plurality of regions formed in a first semiconductor layer and a first wiring layer formed on the first semiconductor layer;

a first insulating layer laminated on the first wiring layer; and

a second integrated circuit constructed so as to include a plurality of regions formed in a second semiconductor layer laminated on the first insulating layer and a second wiring layer formed on the second semiconductor layer,

wherein the first integrated circuit and the second integrated circuit are electrically connected by means of wiring penetrating in a laminated direction, and at least one of two-way data communication between the first integrated circuit and the second integrated circuit, supply of a control signal and supply of a clock signal is carried out via the penetrating wiring.

2. The three-dimensional structural semiconductor device as claimed in claim 1, wherein one or more layered structure in which an insulating layer, a semiconductor layer and a wiring layer are laminated on the second wiring layer in this order is formed;

an integrated circuit including a plurality of regions formed in the semiconductor layer of the layered structure and a wiring layer of the layered structure is configured;

the penetration wiring penetrates the semiconductor layer and the wiring layer of the layered structure in the laminated direction to be electrically connected to the integrated circuit in each group; and

at least one of two-way data communication, control signal communication, and supply of a clock signal among the first integrated circuit, the second integrated circuit, and the integrated circuit of the layered structure is carried out via the penetration wiring.

3. The three-dimensional structural semiconductor device as claimed in claim 1, wherein the first wiring layer and the second wiring layer include a multilayer wiring layer.

4. The three-dimensional structural semiconductor device as claimed in claim 1, wherein the regions formed on the semiconductor layers include a source region, a drain region and a channel region of an insulated gate transistor.

5. The three-dimensional structural semiconductor device as claimed in claim 1, wherein any of the two-way data communication, the control signal communication, and the supply of a clock signal is adapted to be carried out via the penetrating wiring.

6. The three-dimensional structural semiconductor device as claimed in claim 1, wherein the penetration wiring is arranged on a central portion of the first semiconductor layer.

7. The three-dimensional structural semiconductor device as claimed in claim 1, wherein a buffer circuit is inserted on the way of the penetration wiring.

8. The three-dimensional structural semiconductor device as claimed in claim 1, wherein each of the first integrated circuit and the second integrated circuit includes one or more specific circuit.

9. The three-dimensional structural semiconductor device as claimed in claim 2, wherein each of the first integrated circuit, the second integrated circuit, and the integrated circuit of the layered structure includes a plurality of specific circuits.

10. The three-dimensional structural semiconductor device as claimed in claim 8, wherein the penetration wiring is electrically connected to each of the specific circuits via a bus interface.

11. The three-dimensional structural semiconductor device as claimed in claim 8, wherein the specific circuit is constructed from any one of a CPU, a memory, a dedicated hard logic and an external interface.

12. The three-dimensional structural semiconductor device as claimed in claim 1, wherein each of the first integrated circuit and the second integrated circuit is constructed from at least one of a digital circuit, an analog circuit, and a digital-analog mixed circuit.

13. The three-dimensional structural semiconductor device as claimed in claim 1, wherein in addition to the penetration wiring, the first wiring layer and the second wiring layer are connected by means of local bus wiring for carrying out two-way local data communication between the first integrated circuit and the second integrated circuit.

14. The three-dimensional structural semiconductor device as claimed in claim 1, wherein the penetration wiring is formed from at least one of materials composed of metallic materials and carbon.

15. The three-dimensional structural semiconductor device as claimed in claim 1, wherein the first insulating layer is formed from at least one of an oxide, a nitride and a carbon compound whose dielectric constant is less than five.

16. The three-dimensional structural semiconductor device as claimed in claim 1, wherein the first insulating layer is formed from at least one of CFx (x<

4), CHx and a porous material whose dielectric constant is 2.5 or less.

17. A three-dimensional structural semiconductor device, comprising:

a first integrated circuit constructed so as to include a plurality of regions formed in a first semiconductor layer and a first wiring layer formed on the first semiconductor layer;

a first insulating layer laminated on the first wiring layer;

a second integrated circuit constructed so as to include a plurality of regions formed on a second semiconductor layer laminated on the first insulating layer and a second wiring layer formed on the second semiconductor layer; and

penetration bus wiring that penetrates the first semiconductor layer and the second semiconductor layer in a laminated direction to electrically connect the first integrated circuit to the second integrated circuit.

18. A method of manufacturing a three-dimensional structural semiconductor device, the method comprising:

forming a first integrated circuit constructed so as to include a plurality of regions formed in a first semiconductor layer and a first wiring layer formed on the first semiconductor layer;

forming a second integrated circuit constructed so as to include a plurality of regions formed on a second semiconductor layer laminated on a first insulating layer laminated on the first wiring layer, and a second wiring layer formed on the second semiconductor layer;

forming penetration wiring that penetrates the first semiconductor layer and the second semiconductor layer in a laminated direction; and

electrically connecting the first integrated circuit to the second integrated circuit by means of the penetration wiring.