SYSTEM-IN-PACKAGE WITH THROUGH SUBSTRATE VIA HOLES

• US 20100044853A1
• Filed: 01/14/2008
• Published: 02/25/2010
• Est. Priority Date: 01/17/2007
• Status: Abandoned Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Dekker, Ronald, Van Veen, Nicolaas J. A., Yannou, Jean-Marc
• Application Number:
  US12/523,053
• Publication Number:
  US 20100044853A1
• Time in Patent Office: Days
• US Class Current: 257/692
• CPC Class Codes: B81C 1/00087 Holes
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

The present invention relates to a system-in-package that comprises an integration substrate with a thickness of less than 100 micrometer and a plurality of through-substrate vias, which have an aspect ratio larger than 5. A first chip is attached to the integration substrate and arranged between the integration substrate and a support, which is suitable for mechanically supporting the integration substrate during processing and handling. The system-in-package can be fabricated according to the invention without a through-substrate-hole etching step. The large aspect ratio implies reduced lateral extensions, which allow increasing the integration density and decreasing lead inductances.

Claims

1. A system-in-package, comprising:

an integration substrate (with a thickness of less than 100 micrometers and including a first plurality of through-substrate vias, which have an electrically conductive via core and an aspect ratio larger than 5, and which are configured to electrically connect a first conductive element on a first integration-substrate side with a second conductive element on a second integration-substrate side;

a support, which is attached to the integration substrate on its first integration-substrate side and which is suitable for mechanically supporting the integration substrate; and

a first chip, which is attached and electrically connected to the integration substrate either on its first integration-substrate sided, where it is either arranged between the integration substrate and the support or where it forms the support, or

a second chips, which is attached and electrically connected to the integration substrate on its second integration-substrate side.

2. The system-in-package of claim 1, wherein the aspect ratio of the through-substrate vias is between 15 and 25.

3. The system-in-package of claim 1, wherein the integration substrate has a thickness between 15 and 40 Micrometers.

4. The system-in-package of claim 1, comprising a second plurality of trench structures in the integration substrate, which in comparison with the through-substrate vias have smaller depth extensions.

5. The system-in-package of claim 1, comprising at least one trench structure in the integration substrate, which has the same depth extension as the through-substrate vias.

6. The system-in-package of claim 5, wherein the trench structure, as seen in a top view from the first integration-substrate side, has a ring shape.

7. The system-in-package of claim 5, wherein the trench structure forms a section of a cavity in the integration substrate.

8. The system-in-package of claim 1, wherein the through-substrate vias have a via-insulation layer, which is arranged to prevent a direct electrical connection between the via core and the integration substrate.

9. The system-in-package of claim 1, wherein a subset of the first plurality of through-substrate vias is electrically connected to a single contact element on the second integration-substrate sided.

10. The system-in-package of claim 1, comprising an opening in the integration substrate that is open to the second integration-substrate side.

11. The system-in-package of claim 10, wherein a third chip is arranged in the opening.

12. A system-in-package, comprising:

an integration substrate with a thickness of less than 100 micrometers and including through-substrate vias that have an electrically conductive via core, of which vias a first number are configured to electrically connect a first conductive element on the first integration-substrate side with a second conductive element on the second integration-substrate side and of which vias at least one second via is configured to constitute a lateral enclosure for a first portion of the integration substrate;

a support, which is attached to the integration substrate on its first integration-substrate side and which is suitable for mechanically supporting the integration substrates; and

a first chip, which is attached and electrically connected to the integration substrate either on its first integration-substrate side, where it is either arranged between the integration substrate and the support or where it forms the support, or a second chip, which is attached and electrically connected to the integration substrate on its second integration-substrate side.

13. The system-in-package of claim 12, wherein the trench structures are provided with an electrically insulating side wall and the lateral enclosure is configured to electrically isolate the first portion.

14. The system-in-package of claim 13, wherein the lateral enclosure forms at least a part of an electrical shield for a component in or on the first portion of the integration substrate.

15. A system-in-packages, comprising:

an integration substrate with a thickness of less than 100 micrometers and including a first plurality of through-substrate vias, that have an electrically conductive via core, of which vias a first plurality are configured to electrically connect a first conductive element on the first integration-substrate side with a second conductive element on the second integration-substrate side;

at least one access channel to a cavity that is defined at and/or on the first integration-substrate side, said access channel extending from the second integration-substrate side parallel to said through-substrate vias;

a support, which is attached to the integration substrate on its first integration-substrate side and which is suitable for mechanically supporting the integration substrate; and

a first chip, which is attached and electrically connected to the integration substrate on its first integration-substrate side, where it is either arranged between the integration substrate and the support or where it forms the support, or a second chip, which is attached and electrically connected to the integration substrate on its second integration-substrate side.

16. A method for fabricating a system-in-package, comprising:

providing an integration substrate of a thickness, the integration substrate having a first integration-substrate side and a second integration-substrate side and trench structures, such that in the integration substrate of the finished system-in-package an aspect ratio of the through-substrate vias fabricated from the trench structures is larger than 5, a first plurality of which trench structures is provided with an electrically conductive via core;

attaching a support, which is suitable for mechanically supporting the integration substrate at a reduced integration-substrate thickness of less than 100 micrometers, to the integration substrate on its first integration substrate side;

reducing the thickness of the integration substrate from its second integration-substrate side to a thickness below 100 micrometers, such that only a bottom face of the via cores of the via trench structures is exposed;

electrically connecting and attaching a first chip to the integration substrate on its first integration-substrate side, such that the first chip is arranged between the integration substrate and the support, or electrically connecting and attaching a second chip to the integration substrate on its second integration-substrate side.

17. The method of claim 16, comprising:

a fabrication of a second plurality of trench structures in the integration substrate with a smaller depth extension in comparison with a depth extension of the first plurality of trench structures, by reactive ion etching,

wherein the first and second plurality of trench structures are etched concurrently and etching comprises forcing smaller lateral extensions for the second plurality of trench structures than for the first plurality of trench structures.

18. The method of claim 16, wherein thinning the integration substrate comprises:

mechanically grinding the integration substrate from the second integration-substrate side to a thickness that just avoids exposure of the first plurality of trenches;

spin-etching the integration substrate using a first etching agent that leaves the via insulation layer intact;

removing a part of the via-insulation layer by etching, using a second etching agent that leaves the via core intact.

19. The method of claim 16, comprising:

attaching the first chip on the first integration-substrate side of the integration substrate before attaching the supports, and

thinning the first chip before attaching the support.

20. The method of claim 16, wherein attaching the support comprises:

depositing an adhesive layer that can be cured by irradiation with ultraviolet light on the first integration-substrate side;

positioning the support on the adhesive layer;

irradiating the adhesive layer with ultraviolet light.

21. The method of claim 16, comprising a step of fabricating an opening in the integration substrate that is open on the second integration-substrate side.

22. The method of claim 16, comprising a step of attaching and electrically connecting a third chip to the integration substrate in the openings.

23. The method of claim 16, wherein:

providing the integration substrate comprises providing an integration-substrate assembly with the integration substrate having an integration-substrate thickness below 100 micrometers and a temporary support attached thereto; and

reducing the thickness of the integration substrate from its second integration-substrate side to a thickness below 100 micrometers comprises removing the temporary support.

24. A method for manufacturing a system-in-package, comprising the steps of:

providing an integration substrate having a first integration-substrate side and a second integration-substrate side and a thickness and comprising a first plurality of trench structures and a second set of at least one trench structure, all of which trench structures are provided with an electrically conductive via core, of which the first plurality of trench structures is configured for a signal transmission function and of the which second set of trench structures is configured for another function, which is one of a heat dissipation, grounding, lateral enclosure of a first portion of the integration substrate, and constituting at least one access channel for a cavity to be created by removal of a sacrificial layer through said access channel;

attaching a support, which is suitable for mechanically supporting the integration substrate at a reduced integration-substrate thickness of less than 100 micrometers, to the integration substrate on its first integration substrate side;

reducing the thickness of the integration substrate from its second side to a thickness below 100 micrometers, such that only a bottom face of the via cores of the second plurality of trench structures is exposed;

electrically connecting and attaching a first chip to the integration substrate on its first integration-substrate side, such that the first chip is arranged between the integration substrate and the support, or electrically connecting and attaching a second chip to the integration substrate on its second integration-substrate side.

25. An integration substrate including trenches that have an electrically conductive trench core, of which trenches a first plurality are electrically connected with a first conductive element on the first integration-substrate, and of which trenches at least one second trench is configured to constitute a lateral enclosure for a first portion of the integration substrate.