THIN FILM LAMINATION, THIN FILM MAGNETIC SENSOR USING THE THIN FILM LAMINATION AND METHOD FOR MANUFACTURING THE THIN FILM LAMINATION

• US 20100045282A1
• Filed: 11/29/2007
• Published: 02/25/2010
• Est. Priority Date: 11/30/2006
• Status: Active Grant

• Current Assignee: Asahi Kasei Kabushiki Kaisha (Asahi Kasei Corporation)
• Original Assignee: Asahi Kasei Kabushiki Kaisha (Asahi Kasei Corporation)
• Inventors: Okamoto, Atsushi, Shibasaki, Ichiro, Geka, Hirotaka
• Granted Patent: US 8,154,280 B2
• Time in Patent Office: Days
• US Class Current: 324/249
• CPC Class Codes: G01R 33/07 Hall effect devices
• CPC Class Codes: H01L 21/02395 Arsenides
• CPC Class Codes: H01L 21/02463 Arsenides
• CPC Class Codes: H01L 21/02466 Antimonides
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02549 Antimonides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 29/201 including two or more compounds , e.g. alloys H01L29/2006 takes precedence
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/85 Magnetic active materials
• CPC Class Codes: H10N 52/01 Manufacture or treatment
• CPC Class Codes: H10N 52/101 Semiconductor Hall-effect devices
• CPC Class Codes: H10N 52/85 Magnetic active materials
• CPC Class Codes: Y10T 428/12681 Ga-, In-, Tl- or Group VA metal-base component

Abstract

Relating to a thin film lamination and a thin film magnetic sensor using the thin film lamination and a method for manufacturing the thin film lamination that realizes a thin film conducting layer having high electron mobility and sheet resistance as an InAsSb operating layer. A thin film lamination is provided which is characterized by having an Al_xIn_1-xSb mixed crystal layer formed on a substrate, and an InAs_xSb_1-x (0<x≦1) thin film conducting layer directly formed on the Al_xIn_1-xSb layer, in which the Al_xIn_1-xSb mixed crystal layer is a layer that exhibits higher resistance than the InAs_xSb_1-x thin film conducting layer or exhibits insulation or p-type conductivity, and its band gap is greater than the InAs_xSb_1-x thin film conducting layer, and the a lattice mismatch is +1.3% to −0.8%.

Claims

1-21. -21. (canceled)

22. A thin film lamination having mixed crystal layer and thin film conducting layer comprising:

an Al_xIn_1-xSb mixed crystal layer (0.08≦

x≦

1) formed on a substrate; and

an in As_xSb_1-x (0<

x≦

1) thin film conducting layer formed directly on the Al_xIn_1-xSb mixed crystal layer, wherein

the Al_xIn_1-xSb mixed crystal layer is a layer that exhibits higher resistance than the InAs_xSb_1-x thin film conducting layer or that exhibits insulation or p-type conductivity, and by having a band gap greater than the InAs_xSb_1-x thin film conducting layer and by having a lattice mismatch of +1.3% to −

0.8%.

23. The thin film lamination according to claim 22, wherein the Al_xIn_1-xSb mixed crystal layer having percentage (x) of content of Al atoms of 8% to 30% (0.08≦

x≦

0.3).

24. The thin film lamination according to claim 22, wherein the InAs_xSb_1-x thin film conducting layer is doped with at least one of Te, S, Se, Sn, Si and Ge, which belong to VI group atoms or IV group atoms as donor impurities.

25. The thin film lamination according to claim 22, wherein the full width at half maximum of X-ray diffraction of the Al_xIn_1-xSb mixed crystal layer or of the Al_xGa_yIn_1-x-ySb mixed crystal layer is 50 seconds to 1,000 seconds.

26. The thin film lamination according to claim 22, wherein a lattice mismatch between the Al_xIn_1-xSb mixed crystal layer or the Al_xGa_yIn_1-x-ySb mixed crystal layer and the InAs_xSb_1-x thin film conducting layer is +1.3% to −

0.8%.

27. The thin film lamination according to claim 22, wherein a lattice mismatch between the Al_xIn_1-xSb mixed crystal layer or the Al_xGa_yIn_1-x-ySb mixed crystal layer and the InAs_xSb_1-x thin film conducting layer is ±

0.2% or less.

28. The thin film lamination according to claim 22, wherein the in As_xSb_1-x (0<

x≦

1) thin film conducting layer having a film thickness of 100 nm or less and 10 nm or more and electron mobility of 30,000 cm²/Vs or more.

29. The thin film lamination according to claim 22, comprising:

the substrate is a GaAs substrate;

the Al_xIn_1-xSb mixed crystal layer is an Al_0.1In_0.9Sb mixed crystal layer; and

the InAs_xSb_1-x thin film conducting layer is an InAs_0.09Sb_0.91 thin film conducting layer.

30. The thin film lamination according to claim 22, comprising:

an Al_xIn_1-xSb mixed crystal layer (0.08≦

x≦

1) or an Al_xGa_yIn_1-x-ySb mixed crystal layer (0<

x+y≦

1, x≠

0) directly formed on the InAs_xSb_1-x (0<

x≦

1) thin film conducting layer as a cap layer, wherein

the Al_xIn_1-xSb mixed crystal layer cap layer or the Al_xGa_yIn_1-x-ySb mixed crystal layer cap layer is a layer that exhibits higher resistance than the InAs_xSb_1-x thin film conducting layer or that exhibits insulation or p-type conductivity, and by having a band gap greater than the InAs_xSb_1-x thin film conducting layer, and by having a lattice mismatch of +1.3% to −

0.8% with the InAs_xSb_1-x thin film conducting layer.

31. The thin film lamination according to claim 30, comprising:

the substrate is a GaAs substrate;

the Al_xIn_1-xSb mixed crystal layer is an Al_0.1In_0.9Sb mixed crystal layer;

the InAs_xSb_1-x thin film conducting layer is an InAs_0.09Sb_0.91 thin film conducting layer; and

the Al_xIn_1-xSb mixed crystal layer of the cap layer is an Al_0.1In_0.9Sb mixed crystal layer, wherein

further comprising a GaAs protective film on the cap layer of the Al_0.1In_0.9Sb mixed crystal layer as a cap layer.

32. The thin film lamination according to claim 22, comprising:

a GaAs insulating layer is formed on the substrate;

the AlInSb mixed crystal layer is formed thereon;

the InAsSb conducting layer is formed next;

an AlInSb layer is further formed on the InAsSb conducting layer as a cap layer; and

an insulating thin GaAs cap layer is further formed on the AlInSb cap layer.

44. A thin film magnetic sensor characterized by employing the InAs_xSb_1-x thin film conducting layer of the thin film lamination according to claim 22 as an operating layer.

45. The thin film magnetic sensor according to claim 44, wherein the thin film magnetic sensor and a Si integrated circuit chip for amplifying a sensor signal of the thin film magnetic sensor are electrically connected, and are put into a single package.

46. A thin film magnetic sensor characterized by employing the InAs_xSb_1-x thin film conducting layer of the thin film lamination according to claim 24 as an operating layer.

47. The thin film magnetic sensor according to claim 46, wherein the thin film magnetic sensor and a Si integrated circuit chip for amplifying a sensor signal of the thin film magnetic sensor are electrically connected, and are put into a single package.

48. A thin film magnetic sensor characterized by employing the thin film conducting layer in the thin film lamination according to claim 22 as an operating layer of an element utilizing Hall effect or of an element utilizing magnetic resistance effect.

49. The thin film magnetic sensor according to claim 48, wherein the thin film magnetic sensor and a Si integrated circuit chip for amplifying a sensor signal of the thin film magnetic sensor are electrically connected, and are put into a single package.

50. A thin film magnetic sensor characterized by employing the thin film conducting layer in the thin film lamination according to claim 24 as an operating layer of an element utilizing Hall effect or of an element utilizing magnetic resistance effect.

51. The thin film magnetic sensor according to claim 50, wherein the thin film magnetic sensor and a Si integrated circuit chip for amplifying a sensor signal of the thin film magnetic sensor are electrically connected, and are put into a single package.

33. A thin film lamination having mixed crystal layer and thin film conducting layer comprising:

an Al_xGa_1-x-ySb mixed crystal layer (0<

x+y≦

1, x≠

0) formed on a substrate; and

an InAs_xSb_1-x (0<

x≦

1) thin film conducting layer directly formed on the Al_x Ga_yIn_1-x-ySb mixed crystal layer, wherein

the Al_xGa_yIn_1-x-ySb mixed crystal layer is a layer that exhibits higher resistance than the InAs_xSb_1-x thin film conducting layer or that exhibits insulation or p-type conductivity, and by having a band gap greater than the InAs_xSb_1-x thin film conducting layer and by having a lattice mismatch of +1.3% to −

0.8% with the InAs_xSb_1-x thin film conducting layer.

34. The thin film lamination according to claim 33, wherein the Al_xGa_yIn_1-x-ySb mixed crystal layer having percentage (x+y) of content of Al and Ga atoms of 8.0% to 30% (0.08≦

x+y≦

0.3).

35. The thin film lamination according to claim 33, wherein the InAs_xSb_1-x thin film conducting layer is doped with at least one of Te, S, Se, Sn, Si and Ge, which belong to VI group atoms or IV group atoms as donor impurities.

36. The thin film lamination according to claim 33, wherein the full width at half maximum of X-ray diffraction of the Al_xIn_1-xSb mixed crystal layer or of the Al_xGa_yIn_1-x-ySb mixed crystal layer is 50 seconds to 1,000 seconds.

37. The thin film lamination according to claim 33, wherein a lattice mismatch between the Al_xIn_1-xSb mixed crystal layer or the Al_xGa_yIn_1-x-ySb mixed crystal layer and the InAs_xSb_1-x thin film conducting layer is +1.3% to −

0.8%.

38. The thin film lamination according to claim 33, wherein a lattice mismatch between the Al_xIn_1-xSb mixed crystal layer or the Al_xGa_yIn_1-x-ySb mixed crystal layer and the InAs_xSb_1-x thin film conducting layer is 10.2% or less.

39. The thin film lamination according to claim 33, wherein the InAs_xSb_1-x (0<

x≦

1) thin film conducting layer having a film thickness of 100 nm or less and 10 nm or more and electron mobility of 30,000 cm²/Vs or more.

40. The thin film lamination according to claim 33, comprising:

the substrate is a GaAs substrate;

the Al_xIn_1-xSb mixed crystal layer is an Al_0.1In_0.9Sb mixed crystal layer; and

the InAs_xSb_1-x thin film conducting layer is an InAs_0.09Sb_0.91 thin film conducting layer.

41. The thin film lamination according to claim 33, comprising:

an Al_xIn_1-x Sb mixed crystal layer (0.08≦

x≦

1) or an Al_xGa_yIn_1-x-ySb mixed crystal layer (0<

x+y≦

1, x≠

0) directly formed on the InAs_xSb_1-x (0<

x≦

1) thin film conducting layer as a cap layer, wherein

the Al_xIn_1-xSb mixed crystal layer cap layer or the Al_xGa_yIn_1-x-ySb mixed crystal layer cap layer is a layer that exhibits higher resistance than the InAs_xSb_1-x thin film conducting layer or that exhibits insulation or p-type conductivity, and by having a band gap greater than the InAs_xSb_1-x thin film conducting layer, and by having a lattice mismatch of +1.3% to −

0.8% with the InAs_xSb_1-x thin film conducting layer.

42. The thin film lamination according to claim 41, comprising:

the substrate is a GaAs substrate;

the Al_xIn_1-xSb mixed crystal layer is an Al_0.1In_0.9Sb mixed crystal layer;

the InAs_xSb_1-x thin film conducting layer is an InAs_0.09Sb_0.91 thin film conducting layer; and

the Al_xIn_1-xSb mixed crystal layer of the cap layer is an Al_0.1In_0.9Sb mixed crystal layer, wherein

characterized by further comprising a GaAs protective film on the cap layer of the Al_0.1In_0.9Sb mixed crystal layer as a cap layer.

43. The thin film lamination according to claim 33, comprising:

a GaAs insulating layer is formed on the substrate;

the AlInSb mixed crystal layer is formed thereon;

the InAsSb conducting layer is formed next;

an AlInSb layer is further formed on the InAsSb conducting layer as a cap layer; and

an insulating thin GaAs cap layer is further formed on the AlInSb cap layer.

52. A manufacturing method of a thin film lamination having mixed crystal layer and thin film conducting layer comprising

using a molecular beam epitaxy system having a crystal growth chamber capable of maintaining a ultra-high vacuum, a component for heating and evaporating Al, In, Sb and As, or Al, In, Sb, As and Ga in the crystal growth chamber by controlling their vapor pressure independently, a component for heating and evaporating at least one of S, Se, Sn, Si, Ge and Te as donor impurity sources by controlling their vapor pressure independently, a component for holding a crystal growth plane of a substrate at a level substantially, and a component for carrying the substrate in or out of the crystal growth chamber, the manufacturing method of a thin film lamination comprises at least the step of;

growing an insulating AlInSb mixed crystal layer on the substrate by exposing the substrate plane heated at 300 to 500°

C. to vapors of necessary component elements in a condition in which a degree of background vacuum is maintained at 1×

10<sup>−

10</sup> to 1×

10<sup>−

6</sup> Pa (pascal); and

forming an InAsSb thin film conducting layer on the AlInSb mixed crystal layer by epitaxial growth of InAsSb with a lattice mismatch of +1.3% to −

0.8% with the AlInSb mixed crystal layer.

53. The manufacturing method of a thin film lamination according to claim 52, comprising at least the step of:

forming the InAsSb with a lattice mismatch of +1.3% to −

0.8% with the AlInSb mixed crystal layer on the AlInSb mixed crystal layer by epitaxial growth; and

forming and stacking an AlInSb mixed crystal layer with a lattice mismatch of +1.3% to −

0.8% with the InAsSb mixed crystal layer on the InAsSb next.

54. The manufacturing method of a thin film lamination according to claim 53, wherein the substrate is a GaAs substrate, and comprising the step of:

growing the Al_0.1In_0.9Sb mixed crystal layer by 0.7 μ

m on the GaAs substrate;

growing the InAs_0.09Sb_0.91 thin film conducting layer by 0.15 μ

m thereon;

growing the Al_0.1In_0.9Sb mixed crystal layer by 0.05 μ

m as a cap layer, and further forming a 0.0065 μ

m thick GaAs cap layer as a protective film of a top layer.

55. The manufacturing method of a thin film lamination according to claim 52, wherein the substrate is a GaAs substrate, and comprising the step of:

growing the Al_0.1In_0.9Sb mixed crystal layer by 0.7 μ

m on the GaAs substrate;

growing the InAs_0.09Sb_0.91 thin film conducting layer by 0.15 μ

m thereon;

growing the Al_0.1In_0.9Sb mixed crystal layer by 0.05 μ

m as a cap layer, and further forming a 0.0065 μ

m thick GaAs cap layer as a protective film of a top layer.

56. A manufacturing method of a thin film magnetic sensor having mixed crystal layer and thin film conducting layer comprising:

using a molecular beam epitaxy system having a crystal growth chamber capable of maintaining a ultra-high vacuum, a component for heating and evaporating Al, In, Sb and As, or Al, In, Sb, As and Ga in the crystal growth chamber by controlling their vapor pressure independently, a component for heating and evaporating at least one of S, Se, Sn, Si, Ge and Te as donor impurity sources by controlling their vapor pressure independently, a component for holding a crystal growth plane of a substrate at a level substantially, and a component for carrying the substrate in or out of the crystal growth chamber, the manufacturing method of a thin film magnetic sensor comprises at least the step of;

growing an insulating AlInSb mixed crystal layer on the substrate by exposing the substrate plane heated at 300 to 500°

C. to vapors of necessary component elements in a condition in which a degree of background vacuum is maintained at 1×

10<sup>−

10</sup> to 1×

10<sup>−

6</sup> Pa (pascal);

forming an InAsSb thin film conducting layer on the AlInSb mixed crystal layer by epitaxial growth of InAsSb with a lattice mismatch of +1.3% to −

0.8% with the AlInSb mixed crystal layer;

processing the formed InAsSb thin film conducting layer into a necessary magnetic sensor pattern;

forming a plurality of magnetic sensor chips on a wafer simultaneously by forming ohmic electrode metals in the patterned InAsSb thin film conducting layer; and

fabricating individual magnetic sensor chips by cutting off with a dicing saw.

57. A manufacturing method of a thin film magnetic sensor having mixed crystal layer and thin film conducting layer comprising:

using a molecular beam epitaxy system having a crystal growth chamber capable of maintaining a ultra-high vacuum, a component for heating and evaporating Al, In, Sb and As, or Al, In, Sb, As and Ga in the crystal growth chamber by controlling their vapor pressure independently, a component for heating and evaporating at least one of S, Se, Sn, Si, Ge and Te as donor impurity sources by controlling their vapor pressure independently, a component for holding a crystal growth plane of a substrate at a level substantially, and a component for carrying the substrate in or out of the crystal growth chamber, the manufacturing method of a thin film magnetic sensor comprises at least the step of;

growing an insulating AlInSb layer mixed crystal layer on the substrate by exposing the substrate plane heated at 300 to 500°

C. to vapors of necessary component elements in a condition in which a degree of background vacuum is maintained at 1×

10<sup>−

10</sup> to 1×

10<sup>−

6</sup> Pa (pascal);

forming an InAsSb thin film conducting layer on the AlInSb mixed crystal layer by epitaxial growth of InAsSb with a lattice mismatch of +1.3% to −

0.8% with the AlInSb mixed crystal layer;

forming on the InAsSb thin film conducting layer an AlInSb mixed crystal layer constituting a cap layer with a lattice mismatch of +1.3% to −

0.8% with the InAsSb conducting layer and forming a GaAs insulating layer next;

processing the formed InAsSb thin film conducting layer into a necessary magnetic sensor pattern;

forming a plurality of magnetic sensor chips on a wafer simultaneously by forming ohmic electrode metals in a manner as to make ohmic contact with the patterned InAsSb thin film conducting layer; and

fabricating individual magnetic sensor chips by cuffing off with a dicing saw.