HIGH SPEED RECEIVE EQUALIZER ARCHITECTURE

• US 20100046601A1
• Filed: 10/27/2009
• Published: 02/25/2010
• Est. Priority Date: 06/02/2004
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Chung, David, Currivan, Bruce, Momtaz, Afshin, Fujimori, Ichiro, Yin, Guangming, Caresosa, Mario, Tonietto, Davide, Kolze, Thomas
• Granted Patent: US 7,974,337 B2
• Time in Patent Office: Days
• US Class Current: 375/233
• CPC Class Codes: H03G 3/3084 in receivers or transmitters for electromagnetic waves other than radiowaves, e.g. lightwaves H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 2025/03375 Passband transmission
• CPC Class Codes: H04L 2025/03617 Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.

Claims

1. An apparatus comprising:

a continuous time filter configured to filter a signal to provide a filtered signal;

a decision feedback equalizer configured to receive the filtered signal and to generate equalized data signals based on the filtered signal;

a clock and data recovery circuit coupled to the decision feedback equalizer, wherein the clock and data recovery circuit is configured to generate an extracted clock signal from at least a portion of the equalized data signals based on a delay adjust signal; and

an adaptation circuit coupled to the continuous time filter, the decision feedback equalizer, and the clock and data recovery circuit, the adaptation circuit being configured to adapt equalization according to at least one dithering algorithm by adjusting the delay adjust signal based on a mean square error of the equalized data signals.

2. The apparatus of claim 1, wherein the adaptation circuit is configured to adapt the equalization according to the at least one dithering algorithm by adjusting the delay adjust signal based on a change of the mean square error.

3. The apparatus of claim 1, wherein the adaptation circuit is configured to adapt the equalization according to the at least one dithering algorithm by adjusting the delay adjust signal in a same direction as a previous adjustment to the equalization if a mean square error of the equalized data signals decreases and adjusting the delay adjust signal in an opposite direction from the previous adjustment to the equalization if the mean square error of the equalized data signals increases.

4. The apparatus of claim 1, wherein the decision feedback equalizer comprises a retimer configured to generate recovered equalized data signals from the equalized data signals in response to the extracted clock signal.

5. The apparatus of claim 1, further comprising a variable gain amplifier configured to receive an input data and a control signal, the variable gain amplifier being configured to amplify the input data signal based on the control signal to provide the signal to the continuous time filter.

6. The apparatus of claim 1, further comprising:

a variable gain amplifier configured to receive an input data and a control signal from an automatic gain control circuit, the variable gain amplifier being configured to amplify the input data signal based on the control signal to provide the signal to the continuous time filter; and

the automatic gain control circuit configured to receive the filtered signal and to provide the control signal to the variable gain amplifier based on the control signal.

7. The apparatus of claim 1, further comprising a demultiplexer configured to demultiplex the recovered equalized data into a plurality of signals each having a data rate lower than the signal filtered by the continuous time filter.

8. An apparatus comprising:

a continuous time filter coupled to an adaptation circuit, the continuous time filter being configured to filter a signal based on a bandwidth adjust signal received from an adaptation circuit to provide a filtered signal;

a decision feedback equalizer configured to receive the filtered signal and to generate equalized data signals based on the filtered signal, the decision feedback equalizer including a retimer configured to generate recovered equalized data signals from the equalized data signals in response to an extracted clock signal;

a clock and data recovery signal coupled to the decision feedback equalizer and to the adaptation circuit, the clock and data recovery circuit being configured to generate the extracted clock signal from at least a portion of the equalized data signals based on a delay adjust signal received from the adaptation circuit; and

the adaptation circuit coupled to the continuous time filter and the clock and data recovery circuit, the adaptation circuit being configured to adapt equalization in the apparatus according to a least mean square algorithm and at least one dithering algorithm by adjusting at least one of the bandwidth adjust signal and the delay adjust signal based on a mean square error of the equalized data signals.

9. The apparatus of claim 8, wherein the adaptation circuit is configured to adapt the equalization in the apparatus according to the least mean square algorithm and the at least one dithering algorithm by adjusting at least one of the bandwidth adjust signal and the delay adjust signal based on a change of the mean square error of the equalized data signals.

10. The apparatus of claim 8, wherein the adaptation circuit is configured to adapt the equalization in the apparatus according to the least mean square algorithm and the at least one dithering algorithm by adjusting at least one of the bandwidth adjust signal and the delay adjust signal in a same direction as a previous adjustment to the equalization if the mean square error of the equalized data signals decreases and adjusting the at least one of the bandwidth adjust signal and the delay adjust signal in an opposite direction from the previous adjustment to the equalization if the mean square error of the signal based on the equalized data signals increases.

11. The apparatus of claim 8, further comprising an analog to digital converter coupled to the decision feedback equalizer, the analog to digital converter being configured to generate the signal based on the equalized data signals, the signal based on the equalized data signals including at least one digital signal based on the equalized data signals and a clock signal.

12. The apparatus of claim 8, further comprising a variable gain amplifier configured to receive an input signal and a control signal from an automatic gain control circuit, the variable gain amplifier being configured to amplify the input signal based on the control signal to provide the signal to the continuous time filter.

13. The apparatus of claim 8, further comprising:

a variable gain amplifier configured to receive an input signal and a control signal from an automatic gain control circuit, the variable gain amplifier being configured to amplify the input signal based on the control signal to provide the signal to the continuous time filter; and

the automatic gain control circuit configured to receive the filtered signal and to provide the control signal to the variable gain amplifier based on the filtered signal.

14. The apparatus of claim 8, further comprising a delay lock loop configured to generate a clock signal from the extracted clock signal.

15. An apparatus comprising:

means for filtering a signal to provide a filtered signal;

means for generating equalized data signals based on the filtered signal;

means for generating an extracted clock signal from at least a portion of the equalized data signals based on a delay adjust signal; and

means for adapting equalization according to at least one dithering algorithm by adjusting the delay adjust signal based on a mean square error of the equalized data signals.

16. The apparatus of claim 15, wherein the means for adapting equalization include means for adapting the equalization according to the at least one dithering algorithm by adjusting the delay adjust signal based on a change of the mean square error.

17. The apparatus of claim 15, wherein the means for adapting equalization include means for adapting equalization according to the at least one dithering algorithm by adjusting the delay adjust signal in a same direction as a previous adjustment to the equalization if a mean square error of the equalized data signals decreases and adjusting the delay adjust signal in an opposite direction from the previous adjustment to the equalization if the mean square error of the equalized data signals increases.

18. The apparatus of claim 15, further comprising means for generating recovered equalized data signals from the equalized data signals in response to the extracted clock signal.

19. The apparatus of claim 15, further comprising means for amplifying an input data signal based on a control signal to provide the signal to the continuous time filter.

20. The apparatus of claim 15, further comprising means for demultiplexing the recovered equalized data into a plurality of signals each having a data rate lower than the signal filtered by the continuous time filter.