Through Silicon Via Bonding Structure

• US 20100047963A1
• Filed: 08/19/2008
• Published: 02/25/2010
• Est. Priority Date: 08/19/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kai-Ming, Chen, Chen-Shien, Wang, Dean, Lee, Bo-I, Lee, Chien-Hsiun
• Granted Patent: US 8,932,906 B2
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16113 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73103 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/06 : Polymers polymers per se C08; polymer adhesives C09J
• CPC Class Codes: H01L 2924/07025 : Polyimide

Abstract

System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate.

Claims

1. A method for connecting two semiconductor wafers, the method comprising:

providing a first substrate comprising;

a first side and a second side opposite the first side;

a through silicon via through the first substrate and protruding from the second side of the first substrate;

a buffer layer over the second side of the first substrate;

providing a second substrate with a third side, the second substrate comprising;

a contact on the third side of the second substrate;

a protective layer over the third side of the second substrate;

contacting the buffer layer to the protective layer such that the through silicon via and the contact are aligned with each other; and

bonding the first substrate to the second substrate.

2. The method of claim 1, wherein the bonding the first substrate to the second substrate is performed at least in part through thermo compression bonding.

3. The method of claim 2, wherein the thermo compression bonding is performed at least in part at a temperature of between about 150°

C. and about 400°

C.

4. The method of claim 1, wherein the buffer layer and the protective layer comprise different materials.

5. The method of claim 1, further comprising:

partially curing the buffer layer and the protective layer prior to contacting the buffer layer to the protective layer; and

fully curing the buffer layer and the protective layer subsequent to bonding the first substrate to the second substrate.

6. The method of claim 4, wherein the partially curing the buffer layer is continued until the buffer layer is between about 70% and about 90% cured.

7. The method of claim 1, further comprising reflowing the contact subsequent to contacting the buffer layer to the protective layer.

8. A method for joining two semiconductor substrates, the method comprising:

providing a first substrate with a first surface and a second surface opposite the first surface;

forming an opening through the first substrate extending between the first surface to the second surface;

forming a conductor in the opening and protruding from the second surface of the first substrate;

forming a buffer layer over the second surface of the first substrate, the conductor protruding from the buffer layer;

providing a second substrate with a third surface;

forming a contact bump on the third surface;

forming a protective layer over the third surface such that the contact bump is substantially exposed;

aligning the contact bump and the conductor such that the buffer layer is in contact with the protective layer and the contact bump is in contact with the conductor; and

bonding the protective layer to the buffer layer.

9. The method of claim 8, further comprising forming a liner in the opening prior to forming a conductor.

10. The method of claim 8, wherein the bonding is performed at least in part through thermo-compression.

11. The method of claim 10, wherein the thermo compression bonding is performed at least in part at a temperature of between about 150°

C. and about 400°

C.

12. The method of claim 8, further comprising reflowing the contact bump after aligning the contact pad and the conductor.

13. The method of claim 8, further comprising partially curing the buffer layer prior to bonding the protective layer to the buffer layer.

14. The method of claim 13, wherein the buffer layer is partially cured to about 70% to 90% of a full cure.

15. The method of claim 8, wherein the buffer layer comprises either benzocyclobutene or polyimide.

16. A method for attaching two semiconductor substrates, the method comprising:

providing a first substrate and a second substrate, the first substrate comprising a through silicon via extending from a first side and protruding from a second side opposite the first side, the second substrate comprising a contact on a third side;

forming a protective layer over the third side of the second substrate;

forming a buffer layer over the second side of the first substrate, the through silicon via protruding from the buffer layer;

contacting the buffer layer with the protective layer and the through silicon via with the contact pad;

bonding the buffer layer to the protective layer; and

reflowing the contact over the through silicon via.

17. The method of claim 16, wherein bonding the buffer layer to the protective layer is performed at least in part through thermo-compression bonding.

18. The method of claim 16, further comprising partially curing the protective layer prior to contacting the buffer layer with the protective layer.

19. The method of claim 18, wherein the partially curing the protective layer is continued until the protective layer is at least 70% cured.

20. The method of claim 16, wherein the thermo compression bonding is performed at least in part at a temperature of between about 150°

C. and about 400°

C.