METHOD OF MANUFACTURING THIN FILM TRANSISTOR ARRAY SUBSTRATE

• US 20100047974A1
• Filed: 08/20/2009
• Published: 02/25/2010
• Est. Priority Date: 08/21/2008
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Kwack, Hee Young, Lim, Joo Soo
• Granted Patent: US 8,008,139 B2
• Time in Patent Office: Days
• US Class Current: 438/158
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A simplified method of manufacturing a thin film transistor array substrate is disclosed. The method includes: forming gate electrodes, gate lines and gate pads on a substrate with the use of a first mask; forming a gate insulation film, a semiconductor layer, and a metal layer on the substrate; forming a first photoresist pattern on the metal layer with the use of a second mask; forming first contact holes for the gate pads with the use of the first photoresist pattern; forming a second photoresist pattern, and providing patterns for data pads, data lines, and thin film transistors with the use of the second photoresist pattern; providing a third photoresist pattern, and forming contact holes for source/drain electrodes and second contact holes the gate pads with the use of the third photoresist pattern; forming a protective film on the substrate and providing a fourth photoresist pattern on the protective film with the use of a third mask; forming third contact holes for the gate pads, contact holes for the data pads, gate lines, and drain electrodes, and contact holes for pixel electrodes, with the use of the fourth photoresist pattern; and forming a transparent conduction film on the fourth photoresist pattern having the contact holes.

Claims

1. A method of manufacturing a thin film transistor array substrate, comprising:

forming gate electrodes, gate lines and gate pads on a substrate with the use of a first mask;

forming a gate insulation film, a semiconductor layer, and a metal layer on the substrate;

forming a first photoresist pattern on the metal layer with the use of a second mask;

forming first contact holes for the gate pads with the use of the first photoresist pattern;

ashing the first photoresist pattern to form a second photoresist pattern, and forming patterns for data pads, data lines, and thin film transistors with the use of the second photoresist pattern;

ashing the second photoresist pattern to form a third photoresist pattern, and forming contact holes for source/drain electrodes and second contact holes for the gate pads with the use of the third photoresist pattern;

forming a protective film on the substrate and providing a fourth photoresist pattern on the protective film with the use of a third mask;

forming third contact holes for the gate pads, contact holes for the data pads, gate lines, and drain electrodes, and contact holes for pixel electrodes, with the use of the fourth photoresist pattern;

forming a transparent conduction film on the fourth photoresist pattern having the contact holes, to provide first transparent electrodes for the gate pads into the third contact holes, second transparent electrodes into the contact holes for the data pads, third transparent electrodes into the contact holes for the pixel electrodes, fourth transparent electrodes into the contact holes for the gate lines, and fifth transparent electrodes into the contact holes for the drain electrodes; and

removing the fourth photoresist pattern,

wherein the third mask includes transmissive regions transmitting lights, semi-transmissive transmissive regions partially transmitting and intercepting the lights, and interceptive regions intercepting the lights, and the three regions have different transmittances.

2. The method claimed as claim 1, wherein the second mask includes a transmissive region transmitting the lights, first and second semi-transmissive regions partially transmitting and intercepting the lights, and an interceptive region intercepting the lights, and the four regions have different transmittances.

3. The method claimed as claim 1, wherein parts of the fourth photoresist pattern forming the contact holes for the pixel electrodes are opposed to the semi-transmissive regions and transmissive regions of the third mask which is alternately arranged.

4. The method claimed as claim 1, wherein the third transparent electrode is about 1.8˜

2.2 μ

m in width.

5. The method claimed as claim 1, wherein the metal layer includes copper Cu.

6. A method of manufacturing a thin film transistor array substrate, comprising:

forming gate electrodes, gate lines and gate pads on a substrate with the use of a first mask;

forming a gate insulation film, a semiconductor layer, and a metal layer on the substrate;

forming a first photoresist pattern on the metal layer with the use of a second mask;

forming first contact holes for the gate pads, patterns for the gate pads and gate lines, and patterns for data lines and thin film transistors, with the use of the first photoresist pattern;

ashing the first photoresist pattern to form a second photoresist pattern, and forming source/drain electrodes and second contact holes for the gate pads and removing the metal layer of the patterns for the gate pads and lines, with the use of the second photoresist pattern;

forming a protective film on the substrate and providing a third photoresist pattern on the protective film with the use of a third mask;

forming third contact holes for the gate pads, contact holes for pixel electrodes, and contact holes for the gate lines and drain electrodes, with the use of the third photoresist pattern;

forming a transparent conduction film on the third photoresist pattern having the contact holes, to provide first transparent electrodes into the third contact holes for the gate pads, second transparent electrodes into the contact holes for the pixel electrodes, third transparent electrodes into the contact holes for the gate lines, and fourth transparent electrodes into the contact holes for the drain electrodes; and

removing the third photoresist pattern,

wherein the third mask includes transmissive regions transmitting lights, semi-transmissive regions partially transmitting and intercepting the lights, and interceptive regions intercepting the lights, and the three regions have different transmittances.

7. The method claimed as claim 6, wherein parts of the third photoresist pattern forming the contact holes for the pixel electrodes are opposed to the semi-transmissive regions and transmissive regions of the third mask which is alternately arranged.

8. The method claimed as claim 6, wherein parts of the fourth photoresist pattern forming the contact holes for the pixel electrodes are opposed only to the transmissive regions of the third mask.

9. The method claimed as claim 6, wherein the second transparent electrode is about 1.8˜

2.2 μ

m in width.

10. The method claimed as claim 6, wherein the metal layer includes molybdenum Mo.