SEMICONDUCTOR DEVICE GATE STRUCTURE INCLUDING A GETTERING LAYER

• US 20100048010A1
• Filed: 10/23/2008
• Published: 02/25/2010
• Est. Priority Date: 08/21/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Peng-Fu, Hou, Yong-Tian, Chen, Chien-Hao, Chao, Donald Y., Hung, Cheng-Lung, Huang, Kuo-Tai
• Granted Patent: US 7,989,321 B2
• Time in Patent Office: Days
• US Class Current: 438/591
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/3221 of silicon bodies, e.g. for gettering
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane

Abstract

A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and/or restricted from growth.

Claims

1. A method of fabricating a semiconductor device, comprising:

providing a semiconductor substrate;

forming an interface layer on the semiconductor substrate;

forming a gate dielectric layer on the interface layer; and

forming a gettering layer on the gate dielectric layer, wherein the gettering layer includes an oxygen-gettering, dielectric composition.

2. The method of claim 1, wherein the gate dielectric layer includes a high-k dielectric.

3. The method of claim 1, wherein the interface layer includes silicon oxide.

4. The method of claim 1, wherein the gettering layer is selected from a group consisting of SiN, SiON, SiC, SiGe, and combinations thereof.

5. The method of claim 1, wherein the gettering layer includes silicon.

6. The method of claim 1, further comprising:

reducing the thickness of the interface layer, wherein the reducing includes transfer of oxygen from the interface layer to the gettering layer.

7. The method of claim 1, further comprising:

removing the gettering layer; and

forming a gate electrode on the high-k dielectric layer, wherein the gate electrode includes metal.

8. A method of fabricating a gate structure, comprising:

providing a substrate;

forming an interface layer on the substrate, wherein the interface layer includes silicon oxide having a first thickness;

forming a gettering layer overlying the interface layer; and

reducing the thickness of the interface layer to a second thickness by gettering oxygen from the interface layer to the gettering layer.

9. The method of claim 8, wherein the reducing the thickness includes a high temperature process.

10. The method of claim 8, further comprising:

removing the gettering layer; and

depositing a metal layer to form a gate electrode.

11. The method of claim 10, wherein the metal layer is selected from the group consisting of Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, MoN, MoON, RuO₂ and/or combinations thereof.

12. The method of claim 8, wherein the second thickness is less than approximately 5 angstroms.

13. The method of claim 8, further comprising:

forming a metal gate electrode underlying the gettering layer.

14. The method of claim 8, wherein the gettering layer includes an oxygen-gettering dielectric.

15. The method of claim 8, wherein the gettering layer includes an oxygen-gettering metal.

16. A method of semiconductor fabrication, comprising:

providing a semiconductor substrate;

forming an interface layer on the semiconductor substrate;

forming a gate dielectric layer on the interface layer; and

forming a gettering metal layer on the gate dielectric layer, wherein the gettering metal layer includes an oxygen-gettering composition; and

forming a metal gate electrode on the substrate overlying the gate dielectric layer.

17. The method of claim 16, wherein the gettering metal layer includes a metal selected from the group consisting of Ti, Ta, Zr, Hf, W, Mo, and combinations thereof.

18. The method of claim 16, wherein the forming the metal gate electrode includes removing the gettering metal layer.

19. The method of claim 16, wherein the forming the metal gate electrode includes forming the metal gate electrode underlying the gettering metal layer.

20. The method of claim 16, wherein the metal gate electrode includes a metal selected from the group consisting of Ti, TiN, Ta, Ta, TaC, TaSiN, W, WN, MoN, MoON, RuO₂, and combinations thereof.