MASTER/SLAVE PROCESSOR CONFIGURATION WITH FAULT RECOVERY

• US 20100049268A1
• Filed: 02/20/2008
• Published: 02/25/2010
• Est. Priority Date: 02/20/2007
• Status: Abandoned Application

• Current Assignee: Avery Biomedical Devices, Inc.
• Original Assignee: Avery Biomedical Devices, Inc.
• Inventors: Martins, Antonio Garcia
• Application Number:
  US12/528,001
• Publication Number:
  US 20100049268A1
• Time in Patent Office: Days
• US Class Current: 607/9
• CPC Class Codes: G06F 11/2025 using centralised failover control functionality
• CPC Class Codes: G06F 11/2028 eliminating a faulty processor or activating a spare
• CPC Class Codes: G06F 11/2035 without idle spare hardware

Abstract

A fault-tolerant processor device including a master processor and a plurality of operationally coupled slave processors. The master processor sends a command to each of the slave processors to initiate operation to each control a different one of a plurality of operations during fault-free operation. The master processor monitors each of the operations to confirm the fault-free operation. In a case wherein fault-free operation is not confirmed, the master processor identifies a faulty one of the slave processors, disables the faulty slave processor and initiates operation of a fault-free one of the slave processors to control the operations of the faulty slave processor in addition to the operations of the fault-free slave processor. If the master processor determines that both of the slave processors are faulty, the master processor may disable both of the slave processors and control each of the operations independent of the faulty slave processors.

Claims

1. A fault-tolerant processor device comprising:

a master processor; and

a plurality of slave processors operationally coupled to the master processor for performing a plurality of operations, each slave processor performing a unique operation, wherein the master processor is configured to;

send an initiation command to each of the plurality of slave processors to initiate each of the plurality of slave processors corresponding unique operation,

monitor each of the plurality of operations to confirm that the slave processor performing the operation is fault-free,

wherein if the processor being fault-free is not confirmed,

identify and disable the faulty one of the plurality of slave processors,

initiate fault-free slave processor the plurality of slave processors to perform the one of the plurality of operations of the disabled faulty slave processor in addition to the one of the plurality of operations of the fault-free slave processor.

2. The device of claim 1, wherein the master processor is configured to

determine if of the plurality of slave processors are fault-free, and

if not, of the plurality of slave processors performing faulty operations and all of the plurality of operations of the faulty slave processors.

3. The device of claim 1, further comprising a user input/output device operationally coupled to the master processor, wherein the master processor is configured to produce a failure indication on the user input/output device if one of the plurality of slave processors is faulty.

4. The device of claim 1, wherein each of the plurality of slave processors are configured to determine if the master processor sent the initiation command, and

if the initiation command was not sent, the plurality of slave processors are configured to

disable the master processor and perform the plurality of operations without the master processor sending the initiating command.

5. The device of claim 4, wherein the determination of if the master processor sent the initiation command is performed within a predetermined period of time.

6. The device of claim 4, wherein each of the plurality of slave processors is configured to monitor the operations of another of the plurality of slave processors if the master processor is disabled.

7. The device of claim 4, comprising a user input/output device operationally coupled to at least one of the plurality of slave processors,

wherein the least one of the plurality of slave processors is configured to produce a failure indication on the user input/output device if the master processor is faulty.

8. The device of claim 1, wherein each of the plurality of slave processors is configured to acknowledge receipt of the initiation command to the master processor.

9. The device of claim 1, wherein the master processor is configured to examine a timing of each of the plurality of operations to determine if there is fault-free operation.

10. The device of claim 1, wherein the device is arranged for driving a diaphragmatic pacemaker having left and right sides, wherein one of the plurality of operations drives the left side of the diaphragmatic pacemaker, and another one of the plurality of operations drives the right side of the diaphragmatic pacemaker.

11. A method of operating a fault-tolerant processor system having a master processor and a plurality of slave processors operationally coupled to the master processors, the method comprising acts of:

sending an initiation command from the master processor to each of the plurality of slave processors;

initiating operation by the slave processors in response to the initiation command;

each slave processor performing a unique operation of a plurality of operations during fault-free operation;

monitoring each of the plurality of operations to confirm that the slave processors are fault-free; and

if the slave processors being fault-free is not confirmed,

identifying a faulty slave processor of the plurality of slave processors,

disabling the faulty slave processor, and

initiating of a fault-free slave processor of the plurality of slave processors to perform the one of the plurality of operations of the faulty slave processor in addition to the one of the plurality of operations of the fault-free slave processor.

12. The method of claim 11, comprising acts of determining if any of the plurality of slave processors are fault-free, and

if none of the plurality of slave processors are fault-free, disabling all of the plurality of slave processors, and performing each of the plurality of operations by the master processor.

13. The method of claim 11, comprising an act of producing a failure indication if one of the plurality of slave processors is faulty.

14. The method of claim 11, comprising acts of:

determining if the master processor sent the initiation command and

if the initiation command was not sent, disabling the master processor, and initiating operation by the slave processors without interaction from the master processor.

15. The method of claim 14, wherein the act of determining if the master processor sent the initiation command comprises an act of determining if the master processor sent the initiation command within a predetermined period of time.

16. The method of claim 14, comprising an act of monitoring the operations of each of the plurality of slave processors by all of the plurality of slave processors if the master processor is disabled.

17. The method of claim 14, further comprising an act of producing a failure indication if the master processor is faulty.

18. The method of claim 14, wherein the act of monitoring each of the plurality of operations to confirm the fault-free operation comprises an act of examining a timing of each of the plurality of operations.

19. A diaphragmatic pacemaker having at least two sides, the pacemaker comprising:

a master processor; and

a plurality of slave processors operationally coupled to the master processor for performing a plurality of operations, each slave processor performing a different unique operation, wherein the master processor is configured to

send an initiation command to each of the plurality of slave processors to initiate each of the plurality of slave processors corresponding unique operation, each of at least two of the slave processors controlling a corresponding different side of the diaphragmatic pacemaker during fault-free operation,

monitor that each side of the diaphragmatic pacemaker is properly controlled, and

if any side is not properly controlled,

identify and disable a faulty one of the plurality of slave processors performing the improper control, and

initiate of a fault-free slave processor of the plurality of slave processors to control both sides of the diaphragmatic pacemaker.

20. The diaphragmatic pacemaker of claim 19, comprising a user input/output device operationally coupled to the master processor,

wherein the master processor is configured to produce a failure indication if one of the plurality of slave processors is faulty.