TESTABLE ELECTRONIC DEVICE FOR WIRELESS COMMUNICATION

• US 20100049465A1
• Filed: 02/21/2008
• Published: 02/25/2010
• Est. Priority Date: 02/23/2007
• Status: Abandoned Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Roovers, Ralf L.J., Hai, Noman, Gronthoud, Alexander G., Pineda De Gyvez, Jose De Jesus
• Application Number:
  US12/526,852
• Publication Number:
  US 20100049465A1
• Time in Patent Office: Days
• US Class Current: 702/122
• CPC Class Codes: H04B 17/0085 using test signal generators
• CPC Class Codes: H04B 17/15 Performance testing
• CPC Class Codes: H04B 17/17 Detection of non-compliance or faulty performance, e.g. response deviations H04B17/18 takes precedence
• CPC Class Codes: H04B 17/19 Self-testing arrangements

Abstract

An electronic device is disclosed comprising a transceiver stage (140) for communicating signals between the electronic device and a further device; and a baseband processor arrangement (120) implementing a built-in self test arrangement for testing the transceiver channels of the electronic device (100). The built-in self test arrangement further comprises a plurality of records, each record comprising predetermined response deviations to different test signals caused by a parametric fault; and means for selecting those records from the plurality of records for which the predetermined response deviation corresponds to the deviation of the received response. The present invention is based on the realization that a deviation of a response to a test signal from an expected value is dependent on specific parametric faults in specific components in the test signal path and, in addition, on the shape of the test signal. This information is stored in the BIST arrangement and is used to identify a parametric fault, if present, by subjecting the electronic device to a series of test signals.

Claims

1. An electronic device comprising:

a transceiver stage for communicating signals between the electronic device and a further device; and

a baseband processor arrangement implementing a built-in self test arrangement for, in a test mode;

forwarding a test signal to the transceiver stage;

receiving a response to the test signal; and

determining, for the response, a deviation from an expected response to the test signal;

characterized in that the built-in self test arrangement further comprises;

a plurality of records, each record comprising predetermined response deviations to different test signals caused by a parametric fault; and

means for selecting those records from the plurality of records for which the predetermined response deviation corresponds to the deviation of the received response.

2. An electronic device as claimed in claim 1, wherein the built-in self test arrangement is further arranged to:

forward a further test signal to the transceiver stage;

receive a further response to the further test signal;

determine, for the further response, a further deviation from the expected further response to the further test signal; and

deleting those records from the selection of records that comprise a predetermined deviation from the expected response to the further test signal that is different than the determined further deviation.

3. An electronic device as claimed in in claim 1, further comprising:

a frequency upconversion stage for upconverting the frequency of signals from the baseband processor to the transceiver stage;

a frequency downconversion stage for downconverting the frequency of signals from the transceiver stage to the baseband processor; and

a loopback path from a part of the frequency upconversion stage to a corresponding part of the frequency downconversion stage.

4. An electronic device as claimed in claim 3, wherein:

the frequency upconversion stage comprises an upsampling unit, a filter, a signal modulator and an amplifier coupled in series;

the frequency downconversion stage comprises an amplifier, a signal demodulator, a filter and a downsampling unit coupled in series; and

the electronic device comprises at least one of the following loopback paths;

a first loopback path coupling the output of the amplifier in the upconversion stage to the input of the amplifier in the downconversion stage;

a second loopback path coupling the output of the amplifier in the upconversion stage to the input of the signal demodulator in the downconversion stage; and

a third loopback path coupling the output of the filter in the upconversion stage to the input of the filter in the downconversion stage.

5. An electronic device as claimed in claim 3, wherein each loopback path comprises a test attenuator.

6. An electronic device as claimed in claim 3, wherein the frequency upconversion stage and the frequency downconversion stage are arranged to process complex signals, and wherein each loopback path comprises a pair of subpaths for coupling the respective signal paths of the I and Q components of the complex signal through the frequency upconversion stage to the respective signal paths of the I and Q components of the complex signal through the frequency downconversion stage.

7. An electronic device as claimed in claim 1, wherein the built-in self test arrangement is arranged to calculate the error vector magnitude of the response to the test signal.

8. A method of testing an electronic device comprising:

a transceiver stage for communicating signals between the electronic device and a further device; and

a baseband processor arrangement,

the method comprising;

forwarding a test signal to the transceiver stage;

receiving a response to the test signal; and

determining, for the response, the deviation from the expected response to the test signal;

characterized by further comprising;

providing a plurality of records, each record comprising predetermined response deviations to different test signals caused by a parametric fault; and

selecting those records from the plurality of records for which the predetermined response deviation corresponds to the deviation of the received response.

9. A method as claimed in claim 8, further comprising:

forwarding a further test signal from the baseband processor to the transceiver stage;

receiving a further response to the further test signal at the baseband processor;

determining, for the further response, a further deviation from the expected further response to the further test signal; and

deleting those records from the selection of records that comprise a predetermined deviation from the expected response to the further test signal that is different to the determined further deviation.

10. A method as claimed in claim 8, wherein the electronic device further comprises:

a frequency upconversion stage for upconverting the frequency of signals from the baseband processor to the transceiver stage;

a frequency downconversion stage for downconverting the frequency of signals from the transceiver stage to the baseband processor;

the method further comprising;

providing a loopback path from the frequency upconversion stage to a corresponding part of the frequency downconversion stage.

11. A method as claimed in claim 10, wherein the frequency upconversion stage comprises an upsampling unit, a filter, a signal modulator and an amplifier coupled in series;

the frequency downconversion stage comprises an amplifier, a signal demodulator, a filter and a downsampling unit coupled in series; and

wherein the step of providing a loopback path comprises providing at least one of the following loopback paths;

a first loopback path coupling the output of the amplifier in the upconversion stage to the input of the amplifier in the downconversion stage;

a second loopback path coupling the output of the amplifier in the upconversion stage to the input of the signal demodulator in the downconversion stage; and

a third loopback path coupling the output of the filter in the upconversion stage to the input of the filter in the downconversion stage.