Adaptive Mode Switching of Flash Memory Address Mapping Based on Host Usage Characteristics

• US 20100049908A1
• Filed: 10/30/2009
• Published: 02/25/2010
• Est. Priority Date: 12/30/2003
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Sompel, Mark, Conley, Kevin M., Gonzalez, Carlos J.
• Granted Patent: US 8,301,826 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices

Abstract

In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host programming and controller data consolidation patterns, in order to improve performance and reduce wear. Data are programmed into the memory with different degrees of parallelism.

Claims

1. A non-volatile memory system, comprising:

an array of non-volatile memory cells divided into at least two sub-arrays wherein data are simultaneously accessible in each of the at least two sub-arrays, and

data stored within the at least two sub-arrays with at least first and second different interleaving arrangements.

2. The memory system of claim 1, wherein the data simultaneously accessible in each of the at least two sub-arrays include sectors of data, and wherein sectors of data stored within the at least two sub-arrays include:

at least a first set of data sectors identified by a first set of contiguous logical addresses interleaved across said sub-arrays according to the first interleaving arrangement, and

at least a second set of data sectors identified by a second set of contiguous logical addresses interleaved within a single one of the at least two sub-arrays according to the second interleaving arrangement.

3. The memory system of claim 2, wherein indications of the degree of interleaving of sectors of stored data are also stored.

4. The memory system of claim 3, wherein the indications of the degree of interleaving are stored as overhead within the sectors of stored data to which they pertain.

5. The memory system of claim 3, wherein the indications of the degree of interleaving are stored in sectors separate from the sectors of stored data to which they pertain.

6. A method of operating a non-volatile memory array of memory cells, comprising:

storing data with first and second different interleaving arrangements, and

in response to receiving a command to update at least some of the data stored with the first interleaving arrangement that would result in more optimal performance characteristics by being stored with the second interleaving arrangement,

reading data stored with the first interleaving arrangement, and

writing the read data and the updated data into the memory array with the second interleaving arrangement.