Method And Apparatus For Testing Semiconductor Devices With Autonomous Expected Value Generation

• US 20100050029A1
• Filed: 08/19/2008
• Published: 02/25/2010
• Est. Priority Date: 08/19/2008
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Kemmerling, Todd Ryland
• Granted Patent: US 8,095,841 B2
• Time in Patent Office: Days
• US Class Current: 714/724
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 31/31917 Stimuli generation or application of test patterns to the device under test [DUT]
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Abstract

Method and apparatus for testing semiconductor devices with autonomous expected value generation is described. Examples of the invention can relate to apparatus for interfacing a tester and a semiconductor device under test (DUT). An apparatus can include output processing logic configured to receive test result signals from the DUT responsive to testing by the tester, the output processing logic voting a logic value of a majority of the test result signals as a correct logic value; and memory configured to store indications of whether each of the test result signals has the correct logic value.

Claims

1. Apparatus for interfacing a tester and a semiconductor device under test (DUT), comprising:

output processing logic configured to receive test result signals from the DUT responsive to testing by the tester, the output processing logic voting a logic value of a majority of the test result signals as a correct logic value; and

memory configured to store indications of whether each of the test result signals has the correct logic value.

2. The apparatus of claim 1, wherein at least a portion of the output processing logic is implemented using electronics on a probe card assembly.

3. The apparatus of claim 2, wherein a portion of the output processing logic is implemented on the DUT.

4. The apparatus of claim 1, wherein the output processing logic includes voting logic configured to establish the correct logic value responsive to the test result signals and to compare each of the test result signals with the correct logic value to produce the indications.

5. The apparatus of claim 4, wherein the voting logic comprises:

a first adder configured to produce a first sum of logic ‘

1’

values in the test result signals;

a second adder configured to produce a second sum of logic ‘

0’

values in the test result signals; and

a comparator configured to compare the first sum and the second sum and produce the correct logic value.

6. The apparatus of claim 5, wherein the voting logic comprises:

exclusive OR gates configured to compare the test result signals with the correct logic value as produced by the comparator.

7. The apparatus of claim 1, wherein the memory is coupled to at least one test channel for uploading the indications to the tester.

8. The apparatus of claim 7, wherein the indications comprise less data than the test result signals so as to reduce the number of test channels required by the tester.

9. The apparatus of claim 1, wherein the output processing logic further comprises:

voting logic configured to establish the correct logic value responsive to the test result signals and to compare each of the test result signals with the correct logic value to produce a set of output signals; and

combining logic configured to combine the set of output signals and at least one additional set of output signals from at least one additional voting logic to produce the indications.

10. The apparatus of claim 1, wherein the memory is configured to store the indications in response to a control signal from the tester.

11. The apparatus of claim 1, further comprising:

test channels configured to facilitate communication between the tester and the DUT, the test channels only carrying test signals to perform the testing and the indications produced as a result of the testing to the exclusion of providing the correct logic value so as to reduce the number of test channels required by the tester.

12. A test system for testing a semiconductor device under test (DUT), comprising:

test instruments having a tester;

a probe card assembly having test probes configured to contact devices on the DUT;

output processing logic configured to receive test result signals from groups of pins of the DUT responsive to testing by the tester, the output processing logic configured to vote a logic value of a majority of the test result signals for each group of the pins as a correct logic value; and

memory configured to store indications of whether each of the test result signals for each group of the pins has the correct logic value.

13. The test system of claim 12, further comprising:

circuits configured to interface the tester and the plurality of the devices on the DUT, each circuit interfacing with a respective one of the groups of pins;

wherein the output processing logic includes voting logic disposed in each of the circuits; and

wherein the memory includes a memory circuit disposed in each of the circuits.

14. The test system of claim 13, further comprising, for each of the circuits:

a first test channel, coupling the tester to such circuit, configured to provide a test signal; and

at least one additional test channel, coupling the tester to the memory circuit in such circuit, configured to provide indications stored in the memory circuit to the tester.

15. The test system of claim 14, wherein the indications provided to the tester comprise less data than the test result signals received from the DUT so as to reduce the number of test channels on the probe card assembly.

16. The test system of claim 13, further comprising, for each of the circuits:

a second test channel, coupling the tester to the memory circuit in such circuit, configured to provide a control signal to control the memory circuit in such circuit.

17. The test system of claim 13, further comprising:

combining logic configured to receive outputs from the voting logic in a selected plurality of the circuits and to combine such outputs to produce at least a portion of the indications.

18. The test system of claim 13, wherein the voting logic in each of the circuits comprises:

a first adder configured to produce a first sum of logic ‘

1’

values in the test result signals on the group of pins interfacing such circuit;

a second adder configured to produce a second sum of logic ‘

0’

values in the test result signals on the group of pins interfacing such circuit; and

a comparator configured to compare the first sum and the second sum and produce the correct logic value.

19. The test system of claim 18, wherein the voting logic in each of the circuits comprises:

exclusive OR gates configured to compare the test result signals on the group of pins interfacing such circuit with the correct logic value as produced by the comparator.

20. The test system of claim 12, wherein a portion of the output processing logic is implemented on the DUT.

21. The test system of claim 12, further comprising:

test channels on the probe card assembly coupled between the tester and the DUT, the test channels only carrying test signals to perform the testing and the indications produced as a result of the testing to the exclusion of providing each correct logic value so as to reduce the number of test channels on the probe card assembly.

22. A method of testing a semiconductor device under test (DUT), comprising:

providing a test signal to a plurality of devices on the DUT;

capturing values of test result signals generated by the devices on the DUT;

voting a logic value of a majority of the test result signals as a correct logic value;

comparing each of the values of the test result signals with the correct logic value; and

storing indications of whether each of the test result signals has the correct logic value in a memory.

23. The method of claim 22, further comprising:

transmitting the indications to a tester.

24. The method of claim 23, wherein the indications transmitted to the tester comprise less data than the test result signals received from the DUT so as to reduce the number of test channels coupled to the tester.

25. The method of claim 22, wherein the act of voting comprises:

counting a number of logic ‘

1’

values in the test result signals;

defining a logic ‘

1’

value as the correct value in response to the number of logic ‘

1’

values being greater than a number of logic ‘

0’

values; and

defining a logic ‘

0’

value as the correct value in response to the number of logic ‘

1’

values being less than a number of logic ‘

0’

values.

26. A probe card assembly, comprising:

test probes configured to contact one or more devices on a semiconductor device under test (DUT);

output processing logic configured to receive test result signals from groups of pins of the DUT responsive to testing, the output processing logic configured to vote a logic value of a majority of the test result signals for each group of the pins as a correct logic value; and

memory configured to store indications of whether each of the test result signals for each group of the pins has the correct logic value.

27. The probe card assembly of claim 26, further comprising:

circuits coupled to the test probes, each circuit configured to interface with a respective one of the groups of pins;

wherein the output processing logic includes voting logic disposed in each of the circuits; and

wherein the memory includes a memory circuit disposed in each of the circuits.

28. The probe card assembly of claim 27, further comprising, for each of the circuits:

a first test channel configured to provide a test signal; and

at least one additional test channel configured to carry indications stored in the memory circuit.

29. The probe card assembly of claim 28, wherein the indications comprise less data than the test result signals received from the DUT so as to reduce the number of test channels on the probe card assembly.

30. The probe card assembly of claim 26, further comprising:

test channels on the probe card assembly coupled to the test probes, the test channels only carrying test signals to perform the testing and the indications produced as a result of the testing to the exclusion of providing each correct logic value so as to reduce the number of test channels on the probe card assembly,

31-51. -51. (canceled)