TIMING ANALYZING APPARATUS, TIMING ANALYZING METHOD AND PROGRAM THEREOF

• US 20100050141A1
• Filed: 08/06/2009
• Published: 02/25/2010
• Est. Priority Date: 08/20/2008
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: KANNO, KOJI
• Granted Patent: US 8,171,440 B2
• Time in Patent Office: Days
• US Class Current: 716/113
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/396 Clock trees

Abstract

A timing analyzing apparatus according to an exemplary aspect of the invention includes, a storage apparatus which stores a global clock list including information on clock paths inside and outside a partial area of an electronic circuit, and a post layout processing area netlist which is a netlist of the partial area after layout processing of circuits therein is executed; and a timing analyzing unit which calculates the clock skew between two points on the circuits in the partial area, neglecting the clock delay of a common part outside thereof of two clock paths from the clock source, located outside thereof in the electronic circuit, to the two points (CRPR calculation), to judge whether the delay of a clock path and a signal path of the electronic circuit satisfies timing constraints using the calculated clock skew.

Claims

1. A timing analyzing apparatus, comprising:

a storage apparatus which stores a global clock list including information on clock paths inside and outside a partial area of an electronic circuit, and a post layout processing area netlist which is a netlist of the partial area after layout processing of circuits therein is executed; and

a timing analyzing unit which calculates the clock skew between two points on the circuits in the partial area, neglecting the clock delay of a common part outside thereof of two clock paths from the clock source, located outside thereof in the electronic circuit, to the two points (CRPR calculation between the two points), to judge whether the delay of a clock path and a signal path of the electronic circuit satisfies timing constraints using the calculated clock skew.

2. The timing analyzing apparatus according to claim 1, wherein the timing analyzing unit includes:

a netlist merging unit which replaces description on a clock path between a clock tree terminating driver in the post layout processing area netlist and an external clock pin, which is located at a cross point of the periphery of the partial area and a clock path of the electronic circuit, with description in the global clock list on a clock path from the clock source to the clock tree terminating driver, to make an outside area clock path including area netlist;

a delay calculating unit which calculates the delay of the circuit in the partial area, based on the outside area clock path including area netlist, to output inside area circuit delay information; and

a CRPR base timing analyzing unit which carries out the CRPR calculation, based on the inside area circuit delay information and the outside area clock path including area netlist, to judge, using the calculated clock skew, whether the delay of a clock path or the delay of a signal path of the electronic circuit satisfies timing constraints.

3. The timing analyzing apparatus according to claim 1, wherein the timing analyzing unit includes:

a partial area cutting-out unit which removes clock paths of the partial area from the global clock list to make a post area cutting-out processing global clock list;

a clock skew table making unit which carries out the CRPR calculation for each pair of external clock pins, each external clock pin being located at a cross point of the periphery thereof and a clock path of the electronic circuit, based on delay information of the electronic circuit and the post area cutting-out processing global clock list, to store the calculated clock skew for each pair in a clock skew table;

a delay calculating unit which calculates the delay of the circuit in the partial area based on the post layout processing area netlist, to output the calculated delay in inside area circuit delay information; and

a CRPR base timing analyzing unit which obtains

a) delay information of a clock path between a first point in a circuit therein and one external clock pin of an external clock pin pair, and delay information of a clock path between a second point in a circuit therein and the other external clock pin of the pair from the inside area circuit delay information, and

b) clock skew between the external clock pins of the pair from the clock skew table, and

calculates clock skew between the first point and the second point, based on three obtained information to judge, using the calculated clock skew, whether the delay of a clock path or the delay of a signal path of the electronic circuit satisfies timing constraints.

4. The timing analyzing apparatus according to claim 2, comprising:

a global clock distributing unit which is supplied with top netlist, in which the partial area is defined as a macro and a primitive cell is arranged therein, and distributes clock to outside and inside of the macro, and makes a post global clock distributing processing top netlist to store in the storage apparatus as the global clock list;

a macro cutting-out unit which cuts out clock paths of the macro from the post global clock distributing processing top netlist; and

a layout unit which carries out a circuit layout for the cut-out macro and makes a post layout processing macro netlist to store in the storage apparatus as the post layout processing area netlist.

5. The timing analyzing apparatus according to claim 2, comprising:

a partial area cutting-out unit which cuts out clock paths of the partial area from a chip netlist; and

a layout unit which carries out a circuit layout for the cut-out partial area and makes a post layout processing arbitrary area netlist to store in the storage apparatus as the post layout processing area netlist, wherein

the global clock list corresponds to the chip netlist for which processing of arranging a cell and a wiring is carried out inside and outside the partial area of the electronic circuit.

6. The timing analyzing apparatus according to claim 3, comprising:

a global clock distributing unit which is supplied with a top netlist, in which the partial area is defined as a macro and a primitive cell is arranged therein, and distributes a clock to outside and inside of the macro, and makes a post global clock distributing processing top netlist to store in the storage apparatus as the global clock list;

a macro cutting-out unit which cuts out clock paths of the macro from the post global clock distributing processing top netlist to make a post macro cutting-out processing top netlist as the post area cutting-out processing global clock list;

a delay information calculating unit which calculates delay information of the electronic circuit, based on the post global clock distributing processing top netlist; and

a layout unit which carries out a circuit layout for the cut-out macro and makes a post layout processing macro netlist to store in the storage apparatus as the post layout processing area netlist.

7. The timing analyzing apparatus according to claim 3, comprising:

a partial area cutting-out unit which cuts out clock paths of the partial area from the chip netlist to make a post arbitrary area cutting-out processing chip netlist as the post area cutting-out processing global clock list; and

a layout unit which carries out a circuit layout for the cut-out partial area and makes a post layout processing arbitrary area netlist to store in the storage apparatus as the post layout processing area netlist, wherein

the global clock list corresponds to the chip netlist for which processing of arranging a cell and a wiring is carried out inside or outside the partial area of the electronic circuit, and

the storage apparatus stores global clock path delay information which indicates information on the delay of the electronic circuit.

8. A timing analyzing apparatus, comprising:

a first means for storing a global clock list including information on clock paths inside and outside a partial area of an electronic circuit, and a post layout processing area netlist which is a netlist of the partial area after layout processing of circuits therein is executed; and

a second means for calculating the clock skew between two points on the circuits in the partial area, neglecting the clock delay of a common part outside thereof of two clock paths from the clock source, located outside thereof in the electronic circuit, to the two points (CRPR calculation between the two points), to judge whether the delay of a clock path or a signal path of the electronic circuit satisfies timing constraints using the calculated clock skew.

9. The timing analyzing apparatus according to claim 8, wherein the second means includes:

a third means for replacing description on a clock path between a clock tree terminating driver in the post layout processing area netlist and an external clock pin, which is located at a cross point of the periphery of the partial area and a clock path of the electronic circuit, with description in the global clock list on a clock path from the clock source to the clock tree terminating driver, to make an outside area clock path including area netlist;

a forth means for calculating the delay of the circuit in the partial area, based on the outside area clock path including area netlist to output inside area circuit delay information; and

a fifth means for carrying out the CRPR calculation, based on the inside area circuit delay information and the outside area clock path including area netlist, to judge, using the calculated clock skew, whether the delay of a clock path or the delay of a signal path of the electronic circuit satisfies timing constraints.

10. The timing analyzing apparatus according to claim 8, wherein the second means includes:

a sixth means for removing clock paths of the partial area from the global clock list to make a post area cutting-out processing global clock list;

a seventh means for carrying out the CRPR calculation for each pair of external clock pins, each external clock pin being located at a cross point of the periphery thereof and a clock path of the electronic circuit, based on delay information of the electronic circuit and the post area cutting-out processing global clock list, to store the calculated clock skew for each pair in a clock skew table;

a eighth means for calculating the delay of the circuit in the partial area based on the post layout processing area netlist, to output the calculated delay in inside area circuit delay information; and

a ninth means for obtaining

a) delay information of a clock path between a first point in a circuit therein and one external clock pin of an external clock pin pair, and delay information of a clock path between a second point in a circuit therein and the other external clock pin of the pair from the inside area circuit delay information, and

b) clock skew between the external clock pins of the pair from the clock skew table, and

calculating clock skew between the first point and the second point, based on three obtained information to judge, using the calculated clock skew, whether the delay of a clock path or the delay of a signal path of the electronic circuit satisfies timing constraints.

11. A timing analyzing method, comprising:

storing a global clock list including information on clock paths inside and outside a partial area of an electronic circuit, and a post layout processing area netlist which is a netlist of the partial area after layout processing of circuits therein is executed; and

calculating the clock skew between the points on the circuits in the partial area, neglecting the clock delay of a common part outside thereof of two clock paths from the clock source, located outside thereof in the electronic circuit, to the two points (CRPR calculation between the two points), to judge whether the delay of a clock path and a signal path of the electronic circuit satisfies timing constraints using the calculated clock skew.

12. The timing analyzing method according to claim 11, wherein the calculating clock skew includes:

replacing description on a clock path between a clock tree terminating driver in the post layout processing area netlist and an external clock pin, which is located at a cross point of the periphery of the partial area and a clock path of the electronic circuit, with description in the global clock list on a clock path from the clock source to the clock tree terminating driver, to make an outside area clock path including area netlist;

calculating the delay of the circuit in the partial area, based on the outside area clock path including area netlist to output inside area circuit delay information; and

carrying out the CRPR calculation, based on the inside area circuit delay information and the outside area clock path including area netlist, to judge, using the calculated clock skew, whether the delay of a clock path or the delay of a signal path of the electronic circuit satisfies timing constraints.

13. The timing analyzing method according to claim 11, wherein the calculating clock skew includes:

removing clock paths of the partial area from the global clock list to make a post area cutting-out processing global clock list;

carrying out the CRPR calculation for each pair of external clock pins, each external clock pin being located at a cross point of the periphery thereof and a clock path of the electronic circuit, based on delay information of the electronic circuit and the post area cutting-out processing global clock list, to store the calculated clock skew for each pair in a clock skew table;

calculating the delay of the circuit in the partial area based on the post layout processing area netlist, to output the calculated delay in inside area circuit delay information; and

obtaining

a) delay information of a clock path between a first point in a circuit therein and one external clock pin of an external clock pin pair, and delay information of a clock path between a second point in a circuit therein and the other external clock pin of the pair from the inside area circuit delay information, and

b) clock skew between the external clock pins of the pair from the clock skew table, and

calculating clock skew between the first point and the second point, based on three obtained information to judge, using the calculated clock skew, whether the delay of a clock path or the delay of a signal path of the electronic circuit satisfies timing constraints.

14. A computer-readable recording medium recording thereon a program which makes a computer function as:

a storage apparatus which stores a global clock list including information on clock paths inside and outside a partial area of an electronic circuit, and a post layout processing area netlist which is a netlist of the partial area after layout processing of circuits therein is executed; and

a timing analyzing unit which calculates the clock skew between two points on the circuits in the partial area, neglecting the clock delay of a common part outside thereof of two clock paths from the clock source, located outside thereof in the electronic is circuit, to the two points (CRPR calculation between the two points), to judge whether the delay of a clock path and a signal path of the electronic circuit satisfies timing constraints using the calculated clock skew.

15. The computer-readable recording medium according to claim 14, recording thereon the program which makes a computer function as the timing analyzing unit which includes:

a netlist merging unit which replaces description on a clock path between a clock tree terminating driver in the post layout processing area netlist and an external clock pin, which is located at a cross point of the periphery of the partial area and a clock path of the electronic circuit, with description in the global clock list on a clock path from the clock source to the clock tree terminating driver, to make an outside area clock path including area netlist;

a delay calculating unit which calculates the delay of the circuit in the partial area, based on the outside area clock path including area netlist, to output inside area circuit delay information; and

a CRPR base timing analyzing unit which carries out the CRPR calculation, based on the inside area circuit delay information and the outside area clock path including area netlist, to judge, using the calculated clock skew, whether the delay of a clock path or the delay of a signal path of the electronic circuit satisfies timing constraints.

16. The computer-readable recording medium according to claim 14, recording thereon the program which makes a computer function as the timing analyzing unit which includes:

a partial area cutting-out unit which removes clock paths of the partial area from the global clock list to make a post area cutting-out processing global clock list;

a clock skew table making unit which carries out the CRPR calculation for each pair of external clock pins, each external clock pin being located at a cross point of the periphery thereof and a clock path of the electronic circuit, based on delay information of the electronic circuit and the post area cutting-out processing global clock list, to store the calculated clock skew for each pair in a clock skew table;

a delay calculating unit which calculates the delay of the circuit in the partial area based on the post layout processing area netlist, to output the calculated delay in inside area circuit delay information; and

a CRPR base timing analyzing unit which obtains

a) delay information of a clock path between a first point in a circuit therein and one external clock pin of an external clock pin pair, and delay information of a clock path between a second point in a circuit therein and the other external clock pin of the pair from the inside area circuit delay information, and

b) clock skew between the external clock pins of the pair from the clock skew table, and

calculates clock skew between the first point and the second point, based on three obtained information to judge, using the calculated clock skew, whether the delay of a clock path or the delay of a signal path of the electronic circuit satisfies timing constraints.