THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME

• US 20100051934A1
• Filed: 07/16/2009
• Published: 03/04/2010
• Est. Priority Date: 08/26/2008
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Hong-Sick, Lee, Byeong-Jin, Choung, Jong-Hyun, Hong, Sun-Young, Kim, Bong-Kyun, Yang, Dong-Ju, Suh, Nam-Seok, Choi, Young-Joo, Yun, Pil-Sang
• Application Number:
  US12/504,483
• Publication Number:
  US 20100051934A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin film transistor array panel and a method of manufacturing the same are provided according to one or more embodiments. In an embodiment, a method includes: forming a gate line on an insulation substrate; stacking a gate insulating layer, an oxide semiconductor layer, a first barrier layer, and a first copper layer on the gate line; performing a photolithography process on the oxide semiconductor layer, the first barrier layer, and the first copper layer and forming a data line including a source electrode, a drain electrode, and an oxide semiconductor pattern; forming a passivation layer having the contact hole that exposes the drain electrode on the data line and the drain electrode; and forming a pixel electrode that is connected to the drain electrode through the contact hole on the passivation layer, wherein the forming of a data line, a drain electrode, and an oxide semiconductor pattern includes wet etching the first copper layer and then wet etching the first barrier layer and the oxide semiconductor layer.

Claims

1. A thin film transistor (TFT) array panel comprising:

an insulation substrate;

a gate line that is formed on the insulation substrate and that includes a gate electrode;

a gate insulating layer that is formed on the gate line;

an oxide semiconductor that is formed on the gate insulating layer;

a data line that is formed on the oxide semiconductor and that includes a source electrode;

a drain electrode that is formed on the oxide semiconductor and that is opposite to the source electrode at a position corresponding to the gate electrode;

a passivation layer that is formed on the data line and the drain electrode and that has a contact hole that exposes the drain electrode; and

a pixel electrode that is formed on the passivation layer and that is connected to the drain electrode through the contact hole,

wherein the data line and the drain electrode include a first barrier layer and a first copper layer that is formed on the first barrier layer, and the data line and the drain electrode are disposed within an outer line of the oxide semiconductor.

2. The TFT array panel of claim 1, wherein the first barrier layer has an exposed upper surface by escaping from the first copper layer in a portion in which the source electrode and the drain electrode are opposite to each other.

3. The TFT array panel of claim 2, wherein the first barrier layer comprises titanium (Ti), molybdenum (Mo), molybdenum niobium (MoNb), and/or a molybdenum alloy.

4. The TFT array panel of claim 3, wherein the gate line comprises a second barrier layer and a second copper layer on the second barrier layer.

5. The TFT array panel of claim 4, wherein the second barrier layer comprises titanium (Ti), molybdenum (Mo), molybdenum niobium (MoNb), and/or a molybdenum alloy.

6. The TFT array panel of claim 5, wherein a thickness of the first copper layer and the second copper layer is about 2000-30,000 {acute over (Å

)}.

7. The TFT array panel of claim 6, wherein a thickness of the oxide semiconductor is about 300-2000 {acute over (Å

)}, and a thickness of the first barrier layer is about 100-400 {acute over (Å

)}.

8. The TFT array panel of claim 7, wherein the oxide semiconductor includes an oxide of Zn, In, Ga, Sn, or a mixture thereof.

9. The TFT array panel of claim 1, wherein the gate line comprises a second barrier layer and a second copper layer on the second barrier layer.

10. The TFT array panel of claim 9, wherein the second barrier layer comprises titanium (Ti), molybdenum (Mo), molybdenum niobium (MoNb), and/or a molybdenum alloy.

11. The TFT array panel of claim 1, wherein a thickness of the oxide semiconductor is about 300-2000 {acute over (Å

)}, and a thickness of the first barrier layer is about 100-400 {acute over (Å

)}.

12. A method of manufacturing a TFT array panel, comprising:

forming a gate line on an insulation substrate;

stacking a gate insulating layer, an oxide semiconductor layer, a first barrier layer, and a first copper layer on the gate line;

performing a photolithography process of the oxide semiconductor layer, the first barrier layer, and the first copper layer, and forming a data line including a source electrode, a drain electrode, and an oxide semiconductor pattern;

forming a passivation layer having a contact hole that exposes the drain electrode on the data line and the drain electrode; and

forming a pixel electrode that is connected to the drain electrode through the contact hole on the passivation layer,

wherein the forming of a data line, a drain electrode, and an oxide semiconductor pattern comprises wet etching the first copper layer and then wet etching the first barrier layer and the oxide semiconductor layer.

13. The method of claim 12, wherein the forming of a data line, a drain electrode, and an oxide semiconductor pattern comprises:

forming a first photosensitive film pattern including a first portion and a second portion having a smaller thickness than the first portion on the first copper layer;

wet etching the first copper layer using the first photosensitive film pattern as a mask;

wet etching the first barrier layer and the oxide semiconductor layer using the first photosensitive film pattern as a mask;

forming a second photosensitive film pattern by removing the second portion by etching back the first photosensitive film pattern;

wet etching the first copper layer that is exposed by removing the second portion;

dry etching the first barrier layer that is exposed by wet etching the first copper layer; and

removing the second photosensitive film pattern.

14. The method of claim 13, wherein wet etching of the first copper layer is performed using a non-hydro-peroxide type of etchant including water, nitric acid, and ammonium persulfate (APS), or using a hydro-peroxide type of etchant including H₂O and H₂O₂ as an essential element and including an acid and an additive.

15. The method of claim 14, wherein wet etching of the first barrier layer and the oxide semiconductor layer is performed using an etchant including HF.

16. The method of claim 15, wherein an etchant including HF includes water and HF with a concentration ratio of about 1000:

1 to 20;

1.

17. The method of claim 16, wherein wet etching of the first barrier layer and the oxide semiconductor layer is performed for about 10-90 seconds.

18. The method of claim 17, wherein the stacking of a gate insulating layer, an oxide semiconductor layer, a first barrier layer, and a first copper layer on the gate line comprises depositing the oxide semiconductor layer by flowing Ar and O₂ with a flux of 30-100 sccm and 10-90 sccm, respectively, applying a deposition pressure of 0.12-0.5 pa, and supplying power of 1-3 KW.

19. The method of claim 18, wherein the dry etching of the first barrier layer comprises using Cl2 and BCl3 as etching gases.

20. The method of claim 19, wherein the dry etching of the first barrier layer is performed by flowing Cl2 and BCl3 with a flux of 20-l00 sccm and 50-200 sccm, respectively, and supplying source power of 500-1500 W and bias power of 200-500 W.

21. The method of claim 20, wherein the first barrier layer comprises titanium (Ti).

22. The method of claim 20, wherein the forming of a gate line on the insulation substrate comprises:

forming a second barrier layer;

forming a second copper layer on the second barrier layer;

forming a third photosensitive film pattern on the second copper layer;

wet etching the second copper layer using the third photosensitive film pattern as a mask; and

wet etching the second barrier layer using the third photosensitive film pattern as a mask.

23. The method of claim 22, wherein the wet etching of the second copper layer is performed using a non-hydro-peroxide type of etchant including water, nitric acid, and APS, or using a hydro-peroxide type of etchant including H₂O and H₂O₂ as an essential element and including an acid and an additive, and wherein the wet etching of the second barrier layer is performed using a HF aqueous solution.

24. The method of claim 12, wherein the forming of a gate line on the insulation substrate comprises:

forming a second barrier layer;

forming a second copper layer on the second barrier layer;

forming a third photosensitive film pattern on the second copper layer;

wet etching the second copper layer using the third photosensitive film pattern as a mask; and

wet etching the second barrier layer using the third photosensitive film pattern as a mask.

25. The method of claim 24, wherein the wet etching of the second copper layer is performed using a non-hydro-peroxide type of etchant including water, nitric acid, and APS, or using a hydro-peroxide type of etchant including H₂O and H₂O₂ as an essential element and including an acid and an additive, and wherein the wet etching of the second barrier layer is performed using a HF aqueous solution.