LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME

• US 20100051935A1
• Filed: 07/27/2009
• Published: 03/04/2010
• Est. Priority Date: 08/28/2008
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: LEE, Je-Hun, KIM, Do-Hyun
• Granted Patent: US 8,164,152 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A liquid crystal display and a method of manufacturing the same are provided. The liquid crystal display includes an insulating substrate, a gate electrode formed on the insulating substrate, an oxide semiconductor layer formed on the gate electrode, an etch stopper formed on the oxide semiconductor layer in a channel area, a common electrode formed on the insulating substrate, source and drain electrodes separated from each other on the etch stopper and extending to an upper portion of the oxide semiconductor layer, a passivation layer formed on the etch stopper, the common electrode, the source and drain electrodes, and a pixel electrode formed on the passivation layer and connected to the drain electrode.

Claims

1. A liquid crystal display comprising:

an insulating substrate;

a gate electrode formed on the insulating substrate;

an oxide semiconductor layer formed on the gate electrode;

an etch stopper formed on the oxide semiconductor layer in a channel area;

a common electrode formed on the insulating substrate;

source and drain electrodes separated from each other on the etch stopper and extending to an upper portion of the oxide semiconductor layer;

a passivation layer formed on the etch stopper, the common electrode, and the source and drain electrodes; and

a pixel electrode formed on the passivation layer and connected to the drain electrode.

2. The liquid crystal display of claim 1, wherein the oxide semiconductor layer comprises an oxide of a material selected from Zn, In, Ga, Sn, and combinations thereof.

3. The liquid crystal display of claim 1, wherein the source electrode includes a lower source layer and an upper source layer, and the drain electrode includes a lower drain layer and an upper drain layer.

4. The liquid crystal display of claim 3, wherein the lower source layer and the upper source layer have substantially the same patterns with each other, and the lower drain layer and the upper drain layer have substantially the same patterns with each other.

5. The liquid crystal display of claim 3, wherein the lower source layer and the lower drain layer are formed of the same material and from the same layer as the common electrode.

6. The liquid crystal display of claim 5, wherein the lower source layer, the lower drain layer, and the common electrode are made of oxide with indium (In), zinc (Zn), or tin (Sn).

7. The liquid crystal display of claim 3, wherein the upper source layer and the upper drain layer are made of aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), or alloys thereof.

8. The liquid crystal display of claim 1, wherein the etch stopper is made of oxide, nitride, or oxynitride.

9. The liquid crystal display of claim 1, further comprising a common electrode line arranged on the insulating substrate in parallel with the gate electrode, wherein the common electrode line is connected to the common electrode.

10. The liquid crystal display of claim 1, further comprising a common electrode connecting portion for connecting common electrodes formed at adjacent pixels, wherein the common electrode connecting portion is formed of the same material and from the same layer as the common electrode.

11. The liquid crystal display of claim 1, further comprising an additional gate electrode provided on the passivation layer, the additional gate electrode overlapping with the gate electrode.

12. The liquid crystal display of claim 11, wherein the additional gate electrode is connected to the gate electrode through a contact hole formed in the passivation layer.

13. The liquid crystal display of claim 1, wherein the pixel electrode includes a plurality of main field generating portions separated from each other by cut-out portions, and includes connecting portions connecting the plurality of main field generating portions.

14. A liquid crystal display comprising:

an insulating substrate;

a gate electrode formed on the insulating substrate;

an oxide semiconductor layer formed on the gate electrode;

a common electrode formed on the insulating substrate;

source and drain electrodes separated from each other and formed on the oxide semiconductor layer;

a passivation layer formed on the oxide semiconductor layer, the common electrode, and the source and drain electrodes; and

a pixel electrode formed on the passivation layer and connected to the drain electrode.

15. The liquid crystal display of claim 14, wherein the common electrode is made of oxide with indium (In), and the oxide semiconductor layer is made of oxide without indium (In).

16. The liquid crystal display of claim 15, wherein the oxide semiconductor layer is made of oxide with tin (Sn).

17. The liquid crystal display of claim 16, wherein the common electrode is made of ITO or IZO, and the oxide semiconductor layer is made of ZnSnO, GaSnO, or GaZnSnO.

18. The liquid crystal display of claim 14, wherein the source electrode includes a lower source layer and an upper source layer, and the drain electrode includes a lower drain layer and an upper drain layer.

19. The liquid crystal display of claim 18, wherein the lower source layer and the upper source layer have substantially the same patterns with each other, and the lower drain layer and the upper drain layer have substantially the same patterns with each other.

20. The liquid crystal display of claim 18, wherein the lower source layer and the lower drain layer are formed of the same material and from the same layer as the common electrode.

21. The liquid crystal display of claim 14, wherein the pixel electrode includes a plurality of main field generating portions separated from each other by cut-out portions, and includes connecting portions connecting the plurality of main field generating portions.

22. A method of manufacturing a liquid crystal display comprising:

forming a gate electrode on an insulating substrate;

forming an oxide semiconductor layer on the gate electrode;

forming an etch stopper on a channel area of the oxide semiconductor layer;

forming a lower wire layer and an upper wire layer on the resultant structure;

forming a common electrode comprised of the lower wire layer, and source and drain electrodes comprised of the lower wire layer and the upper wire layer, wherein the common electrode, and the source and drain electrodes are formed by etching the lower wire layer and the upper wire layer;

forming a passivation layer on the etch stopper, the common electrode, and the source and drain electrodes; and

forming a pixel electrode on the passivation layer and connected to the drain electrode,

wherein the source and drain electrodes are separated from each other on the etch stopper and extend onto an upper portion of the oxide semiconductor layer.

23. The method of claim 22, wherein the forming of the common electrode, and the source and drain electrodes, comprises:

forming a photoresist film having areas of different thicknesses and exposing the etch stopper and an upper portion of the drain electrode on the upper wire layer;

etching the upper wire layer and the lower wire layer using the photoresist film as an etch mask;

removing the photoresist film from the common electrode; and

removing the upper wire layer from the common electrode.

24. The method of claim 22, wherein in the forming the pixel electrode further comprises forming an additional gate electrode on the passivation layer, wherein the additional gate electrode overlaps the gate electrode.

25. The method of claim 22, wherein the pixel electrode includes a plurality of main field generating portions separated from each other by cut-out portions, and includes connecting portions connecting the plurality of main field generating portions.