DISPLAY DEVICE

• US 20100051941A1
• Filed: 09/02/2009
• Published: 03/04/2010
• Est. Priority Date: 09/02/2008
• Status: Abandoned Application

• Current Assignee: Panasonic Liquid Crystal Display Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Hitachi Displays Limited (Japan Display Incorporated)
• Inventors: TANAKA, Masahiro
• Application Number:
  US12/552,542
• Publication Number:
  US 20100051941A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

A display device in which an OFF current of a thin film transistor formed of metal oxide semiconductor provided to the display device is further lowered thus ensuring the stability of an operation of the thin film transistor is provided. In a display device in which thin film transistors each of which has a semiconductor layer formed of a metal oxide semiconductor layer are mounted on a substrate, a silicon nitride film is arranged between the substrate and the thin film transistors as a barrier layer, and a gate insulation film of the thin film transistor is formed of a silicon nitride film formed by a plasma CVD method.

Claims

1. A display device in which thin film transistors each of which has a semiconductor layer formed of a metal oxide semiconductor layer are mounted on a substrate, wherein

a silicon nitride film is arranged between the substrate and the thin film transistors as a barrier layer, and

a gate insulation film of the thin film transistor is formed of a silicon nitride film formed by a plasma CVD method.

2. A display device according to claim 1, wherein the gate insulation film is formed by a plasma CVD method at a temperature of 300°

C. or more.

3. A display device according to claim 1, wherein the thin film transistor is configured such that a source electrode and a drain electrode are formed on an upper surface of the metal oxide semiconductor layer, and

the metal oxide semiconductor layer, the source electrode and the drain electrode are formed by collective patterning after performing continuous sputtering.

4. A display device according to claim 1, wherein a gate signal line which is connected to a gate electrode of the thin film transistor intersects with a drain signal line which is connected to a drain electrode of the thin film transistor by way of an insulation film, and

the drain signal line is formed in an arcuate pattern as viewed in a plan view at a portion thereof which intersects with the gate signal line.

5. A display device according to claim 1, wherein a gate electrode of the thin film transistor is formed on the metal oxide semiconductor layer by way of the insulation film in an intersecting manner, and

the metal oxide semiconductor layer is formed in an arcuate pattern as viewed in a plan view at a portion thereof which intersects with the gate electrode.

6. A display device according to claim 1, wherein the thin film transistor has a source electrode and a drain electrode thereof formed on an upper surface of the metal oxide semiconductor layer, and

the metal oxide semiconductor layer is formed on a periphery of the source electrode and the drain electrode in a state where the metal oxide semiconductor layer projects outwardly.

7. A display device according to claim 1, wherein each of a source electrode of the thin film transistor, a drain electrode of the thin film transistor, a signal line which is connected to the source electrode, and a signal line which is connected to the drain electrode respectively has a round boundary between an upper surface thereof and a side wall surface thereof which intersects with the upper surface.

8. A display device according to claim 1, wherein a thickness of a gate electrode of the thin film transistor and a thickness of a gate signal line which is connected to the gate electrode are set twice or more as large as a total thickness of a thickness of the metal oxide semiconductor layer and a thickness of a source electrode or a drain electrode.

9. A display device according to claim 1, wherein the display device is an organic EL display device.