THIN FILM TRANSISTOR ARRAY PANEL

• US 20100051957A1
• Filed: 03/11/2009
• Published: 03/04/2010
• Est. Priority Date: 08/26/2008
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Hyung-Jun, KIM, Dong-Gyu, KIM, Sung-Ryul, CHOI, Yong-Mo, CHO, Sung-Haeng
• Granted Patent: US 7,838,886 B2
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

A thin film transistor array panel, in which a middle storage electrode and a storage electrode overlapping a drain electrode of a thin film transistor thereby forming a storage capacitance are formed. Accordingly, sufficient storage capacitance may be formed without a decrease of the aperture ratio and fight transmittance of a liquid crystal display. Also, the capacitance may be sufficiently formed through the connecting member connected to a gate metal layer.

Claims

1. A thin film transistor array panel comprising:

a substrate;

a gate line disposed on the substrate, the gate line including a gate electrode;

a storage electrode line disposed on the substrate, the storage electrode line including a storage electrode;

a gate insulating layer disposed on the gate line and the storage electrode line;

a semiconductor layer disposed on the gate insulating layer;

a data line disposed on the semiconductor layer and the gate insulating layer, the data line including a source electrode;

a drain electrode facing the source electrode on the semiconductor layer;

a lower layer disposed on the drain electrode;

a middle storage electrode disposed on the lower layer, the middle storage electrode overlapping the drain electrode and thereby forming a first storage capacitance;

an upper layer disposed on the middle storage electrode; and

a pixel electrode disposed on the upper layer, the pixel electrode being connected to the drain electrode.

2. The thin film transistor array panel of claim 1, wherein the middle storage electrode overlaps the pixel electrode, thereby forming a second storage capacitance.

3. The thin film transistor array panel of claim 2, wherein the storage electrode overlaps the drain electrode, thereby forming a third storage capacitance.

4. The thin film transistor array panel of claim 3, wherein

the first storage capacitance is in the range of about 1.5-2.5 times the third storage capacitance.

5. The thin film transistor array panel of claim 4, wherein

the second storage capacitance is in the range of about 0.1-0.3 times the first storage capacitance.

6. The thin film transistor array panel of claim 1, wherein an area of the middle storage electrode is smaller than an area of the drain electrode.

7. The thin film transistor array panel of claim 1, wherein the upper layer comprises an organic material.

8. The thin film transistor array panel of claim 7, wherein the upper layer is thicker than the lower layer.

9. The thin film transistor array panel of claim 1, further comprising a color filter disposed between the upper layer and the lower layer.

10. The thin film transistor array panel of claim 9, wherein the middle storage electrode overlaps the pixel electrode, thereby forming the second storage capacitance.

11. The thin film transistor array panel of claim 1, further comprising a light blocking member disposed on the lower layer.

12. The thin film transistor array panel of claim 1, further comprising a middle storage electrode line disposed on the upper layer, the middle storage electrode line being connected to the middle storage electrode.

13. The thin film transistor array panel of claim 12, further comprising a storage voltage supplying line disposed with the same layer as the data line,

wherein the storage voltage supplying line is connected to the middle storage electrode line.

14. The thin film transistor array panel of claim 13, wherein the storage voltage supplying line is connected to the storage electrode line.

15. A thin film transistor array panel comprising:

a substrate including a display area and a peripheral area;

a gate metal layer disposed in the peripheral area of the substrate;

a gate insulating layer disposed on the gate metal layer;

a semiconductor disposed on the gate insulating layer;

a source electrode disposed on the semiconductor;

a first drain electrode facing the source electrode on the semiconductor;

a passivation layer disposed on the first drain electrode; and

a connecting member disposed on the passivation layer, wherein the connecting member overlaps a portion of the source electrode, and is electrically connected to the gate metal layer.

16. The thin film transistor array panel of claim 15, wherein a portion of the gate metal layer overlaps a portion of the source electrode.

17. The thin film transistor array panel of claim 16, wherein the semiconductor comprises one of a polysilicon semiconductor and an oxide semiconductor.

18. The thin film transistor array panel of claim 15, wherein the gate insulating layer comprises a first opening, the passivation layer comprises a second opening positioned at the same position as the first opening, and the contact hole comprises the first opening and the second opening.

19. The thin film transistor array panel of claim 15, wherein the connecting member comprises one of indium tin oxide (ITO) and indium zinc oxide (IZO).

20. The thin film transistor array panel of claim 15, further comprising:

a thin film transistor disposed on the display area; and

a pixel electrode connected to the thin film transistor.