SEMICONDUCTOR STRUCTURES FORMED ON SUBSTRATES AND METHODS OF MANUFACTURING THE SAME
First Claim
1. A semiconductor apparatus, comprising:
- a metal substrate;
a doped silicon layer on the metal substrate;
a semiconductor layer overlying the doped silicon layer; and
semiconductor structures having one or more p-n junctions at least partially within the semiconductor layer formed by using layering, patterning, and doping steps.
2 Assignments
0 Petitions
Accused Products
Abstract
A semiconductor apparatus includes a metal substrate, a doped silicon layer on the metal substrate, a semiconductor layer overlying the doped silicon layer, and semiconductor structures having one or more p-n junctions at least partially within the semiconductor layer formed by using layering, patterning, and doping steps. In an embodiment, the doped silicon layer comprises a heavily doped silicon layer. In another embodiment, the doped silicon region has a thickness that is less than a thickness of a cleavable region formed by ion implantation. In a specific embodiment, the thickness of the cleavable region is about 1-2 um. In another embodiment, the semiconductor layer has a thickness of approximately 10 um. In another embodiment, the semiconductor structures includes a vertical power MOSFET with the metal substrate configured to be a drain terminal contact region.
58 Citations
18 Claims
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1. A semiconductor apparatus, comprising:
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a metal substrate; a doped silicon layer on the metal substrate; a semiconductor layer overlying the doped silicon layer; and semiconductor structures having one or more p-n junctions at least partially within the semiconductor layer formed by using layering, patterning, and doping steps. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor apparatus on a metal substrate, comprising:
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a doped silicon layer having a thickness that is less than a thickness of a cleavable region formed by ion implantation; a semiconductor layer overlying the doped silicon layer; semiconductor structures having one or more p-n junctions at least partially within the semiconductor layer formed by using layering, patterning, and doping steps; and a sufficient amount of metal in contact with the doped silicon layer to form a metal substrate. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification