Semiconductor device having vertical field effect transistor and method of manufacturing the same

• US 20100052055A1
• Filed: 08/11/2009
• Published: 03/04/2010
• Est. Priority Date: 08/27/2008
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Takeuchi, Kiyoshi
• Application Number:
  US12/461,433
• Publication Number:
  US 20100052055A1
• Time in Patent Office: Days
• US Class Current: 257/351
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

A semiconductor device has: an insulating substrate; a first semiconductor layer of a first conductivity type formed on the insulating substrate; a first vertical field effect transistor of the first conductivity type, one of whose source and drain being formed on the first semiconductor layer; a second semiconductor layer of a second conductivity type formed on the insulating substrate; and a second vertical field effect transistor of the second conductivity type, one of whose source and drain being formed on the second semiconductor layer. The first semiconductor layer and the second semiconductor layer are directly in contact with each other.

Claims

1. A semiconductor device comprising:

an insulating substrate;

a first semiconductor layer of a first conductivity type formed on said insulating substrate;

a first vertical field effect transistor of said first conductivity type, one of whose source and drain being formed on said first semiconductor layer;

a second semiconductor layer of a second conductivity type formed on said insulating substrate; and

a second vertical field effect transistor of said second conductivity type, one of whose source and drain being formed on said second semiconductor layer,

wherein said first semiconductor layer and said second semiconductor layer are directly in contact with each other.

2. The semiconductor device according to claim 1, further comprising a first metal layer formed to be in contact with both of said first semiconductor layer and said second semiconductor layer.

3. The semiconductor device according to claim 2,

wherein said first metal layer is formed over a contact boundary between said first semiconductor layer and said second semiconductor layer.

4. The semiconductor device according to claim 2,

wherein at least a part of said first metal layer is formed below an upper surface of said first semiconductor layer and said second semiconductor layer.

5. The semiconductor device according to claim 2,

wherein said first metal layer has:

a first side surface being in contact with said first semiconductor layer;

a second side surface being in contact with said second semiconductor layer; and

a bottom surface being in contact with said first semiconductor layer and said second semiconductor layer.

6. The semiconductor device according to claim 2, further comprising a second metal layer formed to be in contact with any one of said first semiconductor layer and said second semiconductor layer.

7. The semiconductor device according to claim 6,

wherein said first metal layer and said second metal layer are formed in a same layer.