DOWNSIZE POLYSILICON HEIGHT FOR POLYSILICON RESISTOR INTEGRATION OF REPLACEMENT GATE PROCESS

• US 20100052058A1
• Filed: 03/11/2009
• Published: 03/04/2010
• Est. Priority Date: 08/29/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Cheng, Chung-Long, Thei, Kong-Beng, Chuang, Harry, Hsu, Chen-Pin
• Granted Patent: US 8,153,498 B2
• Time in Patent Office: Days
• US Class Current: 257/364
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: Y10S 438/926 Dummy metallization

Abstract

A semiconductor device and method for fabricating a semiconductor device protecting a resistive structure in gate replacement processing is disclosed. The method comprises providing a semiconductor substrate; forming at least one gate structure including a dummy gate over the semiconductor substrate; forming at least one resistive structure including a gate over the semiconductor substrate; exposing a portion of the gate of the at least one resistive structure; forming an etch stop layer over the semiconductor substrate, including over the exposed portion of the gate; removing the dummy gate from the at least one gate structure to create an opening; and forming a metal gate in the opening of the at least one gate structure.

Claims

1. A method for fabricating a semiconductor device, the method comprising:

providing a semiconductor substrate;

forming at least one gate structure including a dummy gate over the semiconductor substrate;

forming at least one resistive structure including a gate over the semiconductor substrate;

exposing a portion of the gate of the at least one resistive structure;

forming an etch stop layer over the semiconductor substrate, including over the exposed portion of the gate;

removing the dummy gate from the at least one gate structure to create an opening; and

forming a metal gate in the opening of the at least one gate structure.

2. The method of claim 1 wherein forming the gate structure including the dummy gate and forming the resistive structure including the gate comprises forming the dummy gate and the gate wherein a top surface of the dummy gate and a top surface of the gate is substantially recessed from a top surface of the gate structure and a top surface of the resistive structure.

3. The method of claim 1 wherein forming the etch stop layer over the semiconductor substrate including over the exposed portion of the gate comprises, thereafter, performing a chemical mechanical polishing on the etch stop layer.

4. The method of claim 1 wherein forming the metal gate in the opening of the at least one gate structure comprises:

forming a first metal layer over the opening;

forming a second metal layer over the first metal layer; and

thereafter, performing a chemical mechanical polishing on the first metal layer and the second metal layer.

5. The method of claim 1 wherein the gate of the at least one resistive structure and the dummy gate of the at least one gate structure comprises polysilicon.

6. The method of claim 1 wherein the gate of the at least one resistive structure comprises a thickness between approximately 200 Å

and 400 Å

.

7. The method of claim 1 wherein the etch stop layer comprises a contact etch stop layer including silicon nitride.

8. The method of claim 1 wherein forming at least one gate structure and forming at least one resistive structure comprises forming a dielectric layer between the semiconductor substrate and the dummy gate and a dielectric layer between the semiconductor substrate and the gate.

9. The method of claim 1 wherein exposing the portion of the gate of the at least one resistive structure comprises removing a hard mask layer disposed over the gate.

10. The method of claim 1 wherein removing the dummy gate from the at least one gate structure to create the opening in the at least one gate structure comprises removing a hard mask layer disposed over the dummy gate.

11. A method for fabricating a semiconductor device, the method comprising:

providing a semiconductor substrate having a first region and a second region;

forming at least one gate structure in the first region over the semiconductor substrate, wherein the gate structure includes a high-k gate dielectric layer, a dummy poly gate, and a hard mask layer;

forming at least one resistive structure in the second region over the semiconductor substrate, wherein the resistive structure comprises a high-k dielectric layer, a poly gate, and a hard mask layer;

removing the hard mask layer from the resistive structure to create a first opening and expose a portion of the poly gate;

forming an etch stop layer over the semiconductor substrate including within the first opening and over the exposed portion of the poly gate;

removing the dummy poly gate and the hard mask layer from the gate structure to create a second opening; and

forming a metal gate in the second opening.

12. The method of claim 11 wherein forming the gate structure and forming the resistive structure comprises forming the dummy poly gate and the poly gate wherein a top surface of the dummy poly gate and a top surface of the poly gate is substantially recessed from a top surface of the gate structure and a top surface of the resistive structure.

13. The method of claim 11 wherein forming the etch stop layer over the semiconductor substrate including within the first opening and over the exposed portion of the poly gate comprises, thereafter, performing a chemical mechanical polishing on the etch stop layer.

14. The method of claim 11 wherein the etch stop layer comprises a contact etch stop layer including silicon nitride.

15. The method of claim 11 wherein forming the metal gate in the second opening comprises:

forming a first metal layer over the second opening;

forming a second metal layer over the first layer; and

thereafter, performing a chemical mechanical polishing on the first metal layer and the second metal layer to planarize the gate structure.

16. The method of claim 11 wherein the hard mask layer comprises a thickness of approximately 1200 Å

.

17. The method of claim 11 wherein the gate structure further comprises a conductive layer formed between the semiconductor substrate and the dummy poly gate.

18. A semiconductor device protecting a resistive structure in the replacement gate process, the semiconductor device comprising:

a semiconductor substrate including a first region and a second region;

a gate structure disposed over the semiconductor substrate in the first region, the gate structure including a metal gate; and

the resistive structure disposed over the semiconductor substrate in the second region, the resistive structure including a poly gate and an etch stop layer disposed over the poly gate.

19. The semiconductor device of claim 18 wherein a top surface of the metal gate and the poly gate is substantially recessed from a top surface of the gate structure and the resistive structure.

20. The semiconductor device of claim 18 wherein the etch stop layer protects the resistive structure during gate replacement processes including gate fill and chemical mechanical polish processes.

21. The semiconductor device of claim 18 wherein the metal gate comprises a first metal layer and a second metal layer.

22. The semiconductor device of claim 18 wherein the gate structure further includes a high-k gate dielectric layer.

23. The semiconductor device of claim 18 wherein the resistive structure further includes a high-k dielectric layer.