SEMICONDUCTOR DEVICE HAVING A SUSPENDED ISOLATING INTERCONNECT

• US 20100052120A1
• Filed: 09/02/2008
• Published: 03/04/2010
• Est. Priority Date: 09/02/2008
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Linear Technology Corporation (Analog Devices, Inc.)
• Inventors: PRUITT, David Alan
• Granted Patent: US 7,902,665 B2
• Time in Patent Office: Days
• US Class Current: 257/666
• CPC Class Codes: H01F 19/08 Transformers having magnetic bias, e.g. for handling pulses
• CPC Class Codes: H01F 2019/085 Transformer for galvanic isolation
• CPC Class Codes: H01F 2027/2814 with only part of the coil or of the winding in the printed circuit board, e.g. the remaining coil or winding sections can be made of wires or sheets
• CPC Class Codes: H01F 38/14 Inductive couplings for wireless supply or distribution of electric power using inductive coupling H02J50/10
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/4823 connecting the wire to a pin of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/48491 : being an additional member attached to the bonding area through an adhesive or solder, e.g. buffer pad
• CPC Class Codes: H01L 2224/48624 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48647 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48655 : Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/48724 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48747 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48755 : Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/48824 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48847 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48855 : Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/49052 : Different loop heights
• CPC Class Codes: H01L 2224/4912 : Layout
• CPC Class Codes: H01L 2224/49175 : Parallel arrangements
• CPC Class Codes: H01L 2224/49176 : Wire connectors having the same loop shape and height
• CPC Class Codes: H01L 2224/4943 : the connecting portions being staggered
• CPC Class Codes: H01L 2224/85455 : Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/4952 : the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/642 : Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor device is configured to provide current and voltage isolation inside an integrated circuit package. The semiconductor device includes first and second semiconductor dies, a first isolating block positioned on the first semiconductor die, and a second isolating block positioned on the second semiconductor die. The semiconductor device also includes a first interconnect coil having a plurality of wires connecting the first semiconductor die to the second isolating block, and a second interconnect coil having a plurality of wires connecting the second semiconductor die to the first isolating block.

Claims

1. A semiconductor device configured to provide current and voltage isolation inside an integrated circuit package, the semiconductor device comprising:

a first semiconductor die and a second semiconductor die;

a first isolating block positioned on the first semiconductor die;

a second isolating block positioned on the second semiconductor die;

a first interconnect coil having a plurality of wires connecting the first semiconductor die to the second isolating block, and

a second interconnect coil having a plurality of wires connecting the second semiconductor die to the first isolating block.

2. The semiconductor device of claim 1, wherein:

the plurality of wires of the first interconnect coil includes a first wire and a second wire, at one end connected to each other via a first conductive trace positioned on the top surface of the second isolating block and, at another end respectively connected to first and second conductive traces positioned on the top surface of the first semiconductor die, each of the first wire and second wire connecting the first semiconductor die to the second isolating block, and

the plurality of wires of the second interconnect coil includes a first wire and a second wire, at one end connected to each other via a first conductive trace positioned on the top surface of the first isolating block and, at another end respectively connected to first and second conductive traces positioned on the top surface of the second semiconductor die, each of the first wire and second wire connecting the second semiconductor die to the first isolating block.

3. The semiconductor device of claim 1, wherein the first and second interconnect coils are isolated from each other and suspended.

4. The semiconductor device of claim 1, wherein the first and second interconnect coils are surrounded by a molding compound.

5. The semiconductor device of claim 1, wherein the first and second interconnect coils are configured to carry high voltages.

6. The semiconductor device of claim 1, wherein the first and second interconnect coils are mutually positioned such that capacitance coupling is created between the first and second interconnect coils.

7. The semiconductor device of claim 1, wherein the first and second interconnect coils are mutually positioned to form a transformer in the semiconductor device.

8. The semiconductor device of claim 1, wherein the first interconnect coil is connected to a source circuit located on the first semiconductor die and the second interconnect coil is connected to a load circuit located on the second semiconductor die such that an alternating current applied to the first interconnect coil via the source circuit induces a current or voltage on the second interconnect coil connected to the load circuit.

9. The semiconductor device of claim 1, wherein the plurality of wires of the second interconnect coil is wrapped around the plurality of wires of the first interconnect coil.

10. The semiconductor device of claim 1, wherein the plurality of wires of the second interconnect coil is inside the plurality of wires of the first interconnect coil.

11. The semiconductor device of claim 1, wherein the plurality of wires of the second interconnect coil is adjacent the plurality of wires of the first interconnect coil.

12. The semiconductor device of claim 2, wherein the plurality of wires of the first interconnect coil further includes a third wire and a fourth wire, at one end connected to each other via a second conductive trace positioned on the top surface of the second isolating block and, at another end the third wire is connected to the second wire via the second conductive trace positioned on the top surface of the first semiconductor die and the fourth wire is connected to a third conductive trace positioned on the top surface of the first semiconductor die.

13. The semiconductor device of claim 2, wherein the plurality of wires of the second interconnect coil further includes a third wire and a fourth wire, at one end connected to each other via a second conductive trace positioned on the top surface of the first isolating block and, at another end the third wire is connected to the second wire via the second conductive trace positioned on the top surface of the second semiconductor die and the fourth wire is connected to a third conductive trace positioned on the top surface of the second semiconductor die.

14. The semiconductor device of claim 2, wherein the conductive traces include nickel-coated copper, nickel-coated aluminum, or aluminum.

15. The semiconductor device of claim 2, wherein the plurality of wires of the first and second interconnect coils are connected to the conductive traces via ball bonds.

16. The semiconductor device of claim 1, wherein the plurality of wires of the first interconnect coil and the plurality of wires of the second interconnect coil are made of copper, gold, or aluminum.

17. The semiconductor device of claim 1, wherein the first semiconductor die includes thereon a first circuit and the second semiconductor die includes thereon a second circuit such that the first and second circuits communicate with each other though the first and second interconnect coils.

18. A semiconductor device configured to provide current and voltage isolation inside an integrated circuit package, the semiconductor device comprising:

a lead frame including a first set of leads and a second set of leads, the first set of leads being isolated from the second set of leads;

a semiconductor die positioned on the lead frame;

an isolating block positioned on the semiconductor die;

a first interconnect coil formed by a first set of wires, the semiconductor die, and the first set of leads; and

a second interconnect coil isolated from the first interconnect coil and formed by a second set of wires, the isolating block, and the second set of leads.

19. The semiconductor device of claim 18, wherein the first and second interconnect coils are configured to enable a printed circuit board connected to the lead frame to communicate with a circuit located on the semiconductor die.

20. The semiconductor device of claim 18, wherein:

the first set of leads includes a first lead and a second lead each of which is conductive and connected to each other at its end tip portion, and

the first set of wires includes a first wire and a second wire, at one end connected to each other via the first lead and the second lead and, at another end respectively connected to first and second conductive traces positioned on the top surface of the semiconductor die.

21. The semiconductor device of claim 20, wherein:

the first set of leads further includes a third lead and a fourth lead each of which is conductive and connected to each other at its end tip portion, and

the first set of wires further includes a third wire and a fourth wire, at one end connected to each other via the third lead and the fourth lead and, at another end the third wire is connected to the second wire via the second conductive trace positioned on the top surface of the semiconductor die and the fourth wire is connected to a third conductive trace positioned on the top surface of the semiconductor die.

22. The semiconductor device of claim 18, wherein:

the second set of leads includes first, second, third, and fourth leads each of which is conductive and the third and fourth leads connect to each other at their end tip portion,

the second set of wires includes first, second, third, and fourth wires,

the first and second wires, at one end connect to each other via a first conductive trace positioned on the top surface of the isolating block and, at another end the first wire connect to the first lead and the second wire connect to the third lead, and

the third and fourth wires, at one end connect to each other via a second conductive trace positioned on the top surface of the isolating block and, at another end the third wire connect to the fourth lead and the fourth wire being connected to second lead.

23. The semiconductor device of claim 18, wherein the first and second interconnect coils are isolated from each other and suspended.

24. The semiconductor device of claim 18, wherein the first and second interconnect coils are surrounded by a molding compound.

25. The semiconductor device of claim 18, wherein the first and second interconnect coils are configured to carry high voltages.

26. The semiconductor device of claim 18, wherein the first and second interconnect coils are mutually positioned such that capacitance coupling is created between the first and second interconnect coils.

27. The semiconductor device of claim 18, wherein the first and second interconnect coils are mutually positioned to form a transformer in the semiconductor device.

28. The semiconductor device of claim 18, wherein the first interconnect coil is connected to a circuit located on the first semiconductor die and the second interconnect coil is connected to a printed circuit board connected to the lead frame, such that the first and second interconnect coils enable the printed circuit board to communicate with the circuit located on the semiconductor die.

29. The semiconductor device of claim 18, wherein the first set of wires of the first interconnect coil is wrapped around the second set of wires of the second interconnect coil.

30. The semiconductor device of claim 18, wherein the first set of wires of the first interconnect coil is inside the second set of wires of the second interconnect coil.

31. The semiconductor device of claim 18, wherein the first set of wires of the first interconnect coil is adjacent to the second set of wires of the second interconnect coil.

32. The semiconductor device of claim 20, wherein the conductive traces include nickel-coated copper, nickel-coated aluminum, or aluminum.

33. The semiconductor device of claim 20, wherein the first set of wires of the first interconnect coils is connected to the conductive traces via ball bonds.

34. The semiconductor device of claim 18, wherein the first set of wires of the first interconnect coil and the second set of wires of the second interconnect coil are made of copper, gold, or aluminum.