3-D INTEGRATED SEMICONDUCTOR DEVICE COMPRISING INTERMEDIATE HEAT SPREADING CAPABILITIES

• US 20100052134A1
• Filed: 07/21/2009
• Published: 03/04/2010
• Est. Priority Date: 08/29/2008
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Werner, Thomas, Feustel, Frank, Grillberger, Michael
• Granted Patent: US 8,080,866 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/02126 Collar structures
• CPC Class Codes: H01L 2224/0215 Material of the auxiliary member
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/051 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07025 : Polyimide
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]

Abstract

In a three-dimensional chip configuration, a heat spreading material may be positioned between adjacent chips and also between a chip and a carrier substrate, thereby significantly enhancing heat dissipation capability. Furthermore, appropriately sized and positioned through holes in the heat spreading material may enable electrical chip-to-chip connections, while responding thermally conductive connectors may extend to the heat sink without actually contacting the corresponding chips.

Claims

1. A semiconductor device, comprising:

a stacked chip configuration, comprising;

a first chip comprising a first substrate and first circuit elements formed above said first substrate;

a second chip comprising a second substrate and second circuit elements formed above said second substrate;

a heat spreading material positioned between said first chip and said second chip and having a plurality of through holes; and

a plurality of electrical connections extending through said plurality of through holes to electrically connect said first and second chips.

2. The semiconductor device of claim 1, wherein said heat spreading material has a lateral dimension that is greater than a lateral dimension of said first chip and said second chip.

3. The semiconductor device of claim 2, further comprising one or more thermally conductive connectors that connect said heat spreading material with a heat sink.

4. The semiconductor device of claim 3, wherein said one or more thermally conductive connectors are provided at a peripheral area of said heat spreading material so as to not be in mechanical contact with said first and second chips.

5. The semiconductor device of claim 1, further comprising a second heat spreading material attached to one of said first and second chips.

6. The semiconductor device of claim 5, further comprising a carrier substrate attached to said second heat spreading material.

7. The semiconductor device of claim 6, further comprising one or more second thermally conductive connectors extending to a heat sink attached to said carrier substrate.

8. The semiconductor device of claim 1, wherein said heat spreading material is attached to at least one of said first and second chips by an electrically insulating adhesive.

9. The semiconductor device of claim 1, wherein said heat spreading material is attached to at least one of said first and second chips by a contact structure connecting to a bump structure formed on said at least one of said first and second chips.

10. The semiconductor device of claim 1, wherein a thickness of said heat spreading material is approximately 50-500 μ

m.

11. The semiconductor device of claim 1, wherein said heat spreading material is an electrically insulating material.

12. The semiconductor device of claim 1, wherein said heat spreading material comprises a metal.

13. A semiconductor device, comprising:

a first chip comprising a first substrate, a plurality of first circuit elements, a first metallization system and a first heat spreading layer; and

a second chip attached to said first chip and comprising a second substrate, a plurality of second circuit elements and a second metallization system, one of said second substrate and said second metallization system being attached to said first heat spreading layer.

14. The semiconductor device of claim 13, further comprising a second heat spreading layer formed above said second substrate.

15. The semiconductor device of claim 14, further comprising a carrier substrate attached to said second heat spreading layer.

16. The semiconductor device of claim 15, further comprising a heat sink attached to said carrier substrate.

17. The semiconductor device of claim 13, further comprising a peripheral chip region that laterally encloses said plurality of first circuit elements and said first metallization system, wherein said heat spreading layer covers said peripheral chip region.

18. The semiconductor device of claim 17, wherein said peripheral chip region has a lateral extension of approximately 100 μ

m or more.

19. A method of forming a three-dimensional semiconductor device, the method comprising:

providing a first chip comprising a first substrate, a plurality of first circuit elements and a first metallization system;

providing a second chip comprising a second substrate, a plurality of second circuit elements and a second metallization system;

attaching a heat spreading material to said first chip; and

attaching said second chip to said heat spreading material so as to obtain a three-dimensional chip configuration.

20. The method of claim 19, wherein attaching said heat spreading material to said first chip comprises attaching said heat spreading material by using at least one of an adhesive and a reflow material.

21. The method of claim 19, further comprising providing through holes in said heat spreading material and establishing electrical connections between said first and second chips by using said through holes when attaching said second chip to said heat spreading material.