PACKAGE STRUCTURE AND PACKAGE SUBSTRATE

• US 20100052148A1
• Filed: 08/14/2009
• Published: 03/04/2010
• Est. Priority Date: 09/03/2008
• Status: Abandoned Application

• Current Assignee: Unimicron Technology Corporation
• Original Assignee: Unimicron Technology Corporation
• Inventors: Hsu, Shih-Ping
• Application Number:
  US12/541,253
• Publication Number:
  US 20100052148A1
• Time in Patent Office: Days
• US Class Current: 257/692
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 : Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13118 : Zinc [Zn] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13164 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/73203 : Bump and layer connectors
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H05K 1/112 : directly combined with via connections
• CPC Class Codes: H05K 2201/094 : Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads using different types of conductors H05K2201/0391
• CPC Class Codes: H05K 2201/09436 : Pads or lands on permanent coating which covers the other conductors
• CPC Class Codes: H05K 2201/09472 : Recessed pad for surface mounting recess in pad H05K2201/09745; Recessed electrode of component
• CPC Class Codes: H05K 2201/09509 : Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2201/10977 : Encapsulated connections applying non-metallic protective coatings for encapsulating mounted components H05K3/284
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

Provided are a package structure and a package substrate, including: a substrate body having a plurality of matrix-arranged electrical contact pads formed on at least one surface thereof, wherein a solder mask layer is formed on said surface and has a plurality of openings for exposing the electrical contact pads, respectively; a first electroless-plated layer disposed on the electrical contact pads, on the walls of the openings and at the peripheries of the openings; and a second electroless-plated layer disposed on the first electroless-plated layer, the first and second electroless-plated layers constituting a recessed electrical connection structure. By forming the even electroless-plated layers on the electrical contact pads. The invention overcomes drawbacks of the prior art, namely breakage of interfaces between solder bumps and electrical contact pads and even damage of the package structure otherwise caused by excessive differences in stress between the solder bumps.

Claims

1. A package structure, comprising:

a substrate body with at least a surface thereof having a plurality of electrical contact pads arranged thereon in a matrix, the surface having a solder mask layer disposed thereon, wherein the solder mask layer has a plurality of openings for exposing the electrical contact pads, respectively;

a first electroless-plated layer disposed on the electrical contact pads, on walls of the openings and at peripheries of the openings;

a second electroless-plated layer disposed on the first electroless-plated layer, the first and second electroless-plated layers constituting a recessed electrical connection structure;

a semiconductor chip having an active surface with a plurality of electrode pads provided thereon; and

a solder material disposed between the electrode pads and the second electroless-plated layer, filled in the recessed electrical connection structure, and electrically connected to the second electroless-plated layer.

2. The structure of claim 1, wherein the first electroless-plated layer is made of copper (Cu).

3. The structure of claim 1, wherein the second electroless-plated layer is made of one of tin (Sn), nickel/palladium/gold (Ni/Pd/Au), and nickel/gold (Ni/Au).

4. The structure of claim 1, further comprising an underfill material filled between the active surface of the semiconductor chip and the solder mask layer.

5. The structure of claim 1, further comprising a plurality of solder bumps disposed on the second electroless-plated layer and connected to the solder material.

6. The structure of claim 5, wherein the solder bumps located in an outer region of the matrix are larger than the solder bumps located in an inner region of the matrix.

7. The structure of claim 5, wherein the solder bumps located in an outer region of the matrix and the solder bumps located in an inner region of the matrix are made of same or different materials.

8. The structure of claim 5, wherein the solder bumps located in an outer region of the matrix have a material stress less than that of the solder bumps located in an inner region of the matrix.

9. The structure of claim 5, wherein the solder bumps located in corner regions of the matrix are larger than the solder bumps located in other regions of the matrix.

10. A package structure, comprising:

a substrate body with at least a surface thereof having a plurality of electrical contact pads arranged thereon in a matrix, the surface having a solder mask layer disposed thereon, wherein the solder mask layer has a plurality of openings for exposing the electrical contact pads, respectively;

a first electroless-plated layer disposed on the electrical contact pads, on the walls of the openings and at peripheries of the openings;

a second electroless-plated layer disposed on the first electroless-plated layer, the first and second electroless-plated layers constituting a recessed electrical connection structure;

a semiconductor chip having an active surface with a plurality of electrode pads provided thereon, wherein a plurality of metal bumps are provided on the electrode pads and the metal bumps extended into the recessed electrical connection structure constituted by the first and second electroless-plated layers; and

a solder material disposed between the metal bumps and the second electroless-plated layer so as for the solder material to be filled in the recessed electrical connection structure and electrically connected to the second electroless-plated layer.

11. The structure of claim 10, wherein the metal bumps are made of one selected from the group consisting of gold (Au), copper (Cu), nickel (Ni), and lead (Pb).

12. A package structure, comprising:

a substrate body having at least a surface with a plurality of electrical contact pads arranged thereon in a matrix, wherein a solder mask layer is disposed on the surface and has a plurality of openings for exposing the electrical contact pads, respectively;

a first electroless-plated layer disposed on the electrical contact pads, on the walls of the openings and at peripheries of the openings;

a second electroless-plated layer disposed on the first electroless-plated layer, the first and second electroless-plated layers constituting a recessed electrical connection structure;

a plurality of solder bumps disposed on the second electroless-plated layer; and

a semiconductor chip having an active surface with a plurality of electrode pads provided thereon, wherein a plurality of metal bumps are provided on the electrode pads and electrically connected to the solder bumps on the second electroless-plated layer.

13. The structure of claim 12, wherein the metal bumps are made of one selected from the group consisting of gold (Au), copper (Cu), nickel (Ni), and lead (Pb).

14. A package substrate, comprising:

a substrate body having at least a surface with a plurality of electrical contact pads arranged thereon in a matrix, wherein a solder mask layer is disposed on the surface and has a plurality of openings for exposing the electrical contact pads, respectively;

a first electroless-plated layer disposed on the electrical contact pads, on the walls of the openings and at peripheries of the openings; and

a second electroless-plated layer disposed on the first electroless-plated layer, the first and second electroless-plated layers constituting a recessed electrical connection structure.

15. The substrate of claim 14, wherein the first electroless-plated layer is made of copper (Cu).

16. The substrate of claim 14, wherein the second electroless-plated layer is made of one of tin (Sn), nickel/palladium/gold (Ni/Pd/Au), and nickel/gold (Ni/Au).

17. The substrate of claim 14, further comprising a plurality of solder bumps disposed on the second electroless-plated layer.

18. The substrate of claim 17, wherein the solder bumps located in an outer region of the matrix are larger than the solder bumps located in an inner region of the matrix.

19. The substrate of claim 17, wherein the solder bumps located in an outer region of the matrix and the solder bumps located in an inner region of the matrix are made of same or different materials.

20. The substrate of claim 17, wherein the solder bumps located in an outer region of the matrix has a material stress less than that of the solder bumps located in an inner region of the matrix.

21. The substrate of claim 17, wherein the solder bumps located in corner regions of the matrix are larger than the solder bumps located in other regions of the matrix.