Compensation of LDO regulator using parallel signal path with fractional frequency response

• US 20100052635A1
• Filed: 08/26/2008
• Published: 03/04/2010
• Est. Priority Date: 08/26/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Wang, Jianbao
• Granted Patent: US 8,115,463 B2
• Time in Patent Office: Days
• US Class Current: 323/280
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

A low drop out (LDO) voltage regulator (10) includes a pass transistor (MP_pass) having a source coupled by an output conductor (4) to a load and a drain coupled to an input voltage to be regulated. An error amplifier (2) has a first input coupled to a reference voltage, a second input connected to a feedback conductor (4A), and an output coupled to a gate of the pass transistor. A parallel path transistor (MP_pa) has a source coupled to the input voltage, a gate coupled to the output (3) of the error amplifier (2), and a drain coupled to the feedback conductor. A feedback resistor (R_f) is coupled between the feedback conductor and the output conductor.

Claims

1. A low drop out (LDO) voltage regulator comprising:

(a) a pass transistor having a first electrode coupled by an output conductor to a load and a second electrode coupled to an input voltage;

(b) an error amplifier having a first input coupled to a reference voltage, a second input connected to a feedback conductor, and an output coupled to a control electrode of the pass transistor;

(c) a parallel path transistor having a first electrode coupled to the input voltage, a control electrode coupled to the output of the error amplifier, and a second electrode coupled to the feedback conductor; and

(d) a feedback resistance coupled between the feedback conductor and the output conductor.

2. The LDO voltage regulator of claim 1 wherein the pass transistor and the parallel path transistor are P-channel MOS transistors, and wherein the first electrodes are sources, the second electrodes are drains, and the control electrodes are gates.

3. The LDO voltage regulator of claim 1 wherein a channel-width-to-channel-length ratio of the parallel path transistor is substantially less than a channel-width-to-channel-length ratio of the pass transistor.

4. The LDO voltage regulator of claim 1 wherein the feedback resistance is a resistance of a feedback resistor is coupled directly between the feedback conductor and the output conductor.

5. The LDO voltage regulator of claim 1 wherein the feedback resistance is coupled to an intermediate conductor of a divider network coupled to the output conductor.

6. The LDO voltage regulator of claim 2 wherein the gate of the parallel path transistor is coupled to the output of the error amplifier by means of an offset voltage source.

7. The LDO voltage regulator of claim 6 wherein the offset voltage source includes an offset resistor coupled between the gate of the pass transistor and the gate of the parallel path transistor, and also includes a first current source coupled to a first terminal of the offset resistor and a second current source coupled to a second terminal of the offset resistor.

8. The LDO voltage regulator of claim 7 including a third current source coupled between the input voltage and the source of the parallel path transistor, a fourth current source coupled to the drain of the parallel path transistor, and a capacitor coupled between the input voltage and the source of the parallel path transistor.

9. The LDO voltage regulator of claim 7 including a third current source coupled between the input voltage and the source of the parallel path transistor, a fourth current source coupled to the drain of the parallel path transistor, and a fractional frequency response network coupled between the input voltage and the source of the parallel path transistor.

10. The LDO voltage regulator of claim 9 wherein the fractional frequency response network includes first, second, and third MOS resistive elements each having a source coupled to the input voltage and a gate coupled to a first bias voltage, and first, second, third, and fourth capacitors, the first capacitor being coupled between the input voltage and a drain of the first MOS resistive element, the second capacitor being coupled between the drain of the first MOS resistive element and a drain of the second MOS resistive element, the third capacitor being coupled between the drain of the second MOS resistive element and a drain of the third MOS resistive element, the fourth capacitor being coupled between the drain of the third MOS resistive element and the source of the parallel path transistor.

11. The LDO voltage regulator of claim 10 including a current limit transistor having a source coupled to the drain of the parallel path transistor, a gate coupled to a second bias voltage, and a drain coupled to the feedback conductor.

12. The LDO voltage regulator of claim 11 wherein the error amplifier includes first and second input transistors having sources coupled to a tail current transistor, a gate of the first input transistor being coupled to the reference voltage, a gate of the second input transistor being coupled to the feedback conductor, a drain of the first input transistor being coupled to a drain and gate of a first load transistor and a gate of a first current mirror output transistor having a drain coupled to a drain and gate of a first current mirror input transistor and a gate of a second current mirror output transistor which functions as the second current source, a drain of the second input transistor being coupled to a drain and gate of a second load transistor and a gate of a third current mirror output transistor which functions as the first current source.

13. The LDO voltage regulator of claim 12 wherein the first and second input transistors, the first current mirror input transistor, and the second current mirror output transistor are N-channel transistors, and wherein the first and second load transistors and the first and third current mirror output transistors are P-channel transistors.

14. The LDO voltage regulator of claim 13 including a P-channel fourth current mirror output transistor coupled between the input voltage and the source of the parallel path transistor functioning as the third current source and having a gate coupled to a gate and drain of a P-channel second current mirror input transistor and a drain of a N-channel fifth current mirror output transistor having a gate coupled to a gate and drain of a N-channel third current mirror input transistor, a N-channel sixth current mirror output transistor and having a drain coupled to the feedback conductor and a gate coupled to the gate and drain of the third current mirror input transistor, a N-channel seventh current mirror output transistor having a gate coupled to the gate and drain of the third current mirror input transistor and a drain coupled to a gate and drain of a first diode-connected P-channel transistor and the gates of the first, second, and third MOS resistive elements, and a N-channel eighth current mirror output transistor having a drain coupled to the gate of the current limit transistor and a gate and drain of a second diode-connected P-channel transistor and a gate coupled to the gate and drain of the third current mirror input transistor, the third current mirror input transistor having its gate and drain coupled to a bias current source.

15. A method of operating a low drop out (LDO) voltage regulator with low quiescent current and at least a predetermined phase margin despite large variations in load current, the method comprising:

(a) applying an input voltage to a first electrode of a pass transistor and coupling a second electrode of the pass transistor to an output conductor applying an output voltage to a load;

(b) coupling a first input of an error amplifier to a reference voltage, and coupling an output of the error amplifier to a control electrode of the pass transistor;

(c) coupling a feedback resistance between the output conductor and a second input of the error amplifier; and

(d) compensating the LDO voltage regulator by coupling a parallel path transistor between the input voltage and the second input of the error amplifier and by coupling a control electrode of the parallel path transistor to the output of the error amplifier.

16. The method of claim 15 including applying an offset voltage between the control electrode of the pass transistor and the control electrode of the parallel path transistor.

17. The method of claim 16 wherein applying the offset voltage includes forcing a current through an offset resistor to generate the offset voltage and coupling a first current source between the input voltage and the first electrode of the parallel path transistor, coupling a fourth current source to the second electrode of the parallel path transistor, and coupling capacitive circuitry between the input voltage and the first electrode of the parallel path transistor.

18. The method of claim 17 providing the capacitive circuitry in the form of a fractional frequency response network coupled between the input voltage and the first electrode of the parallel path transistor.

19. The method of claim 17 including coupling a current limit transistor between the second electrode of the parallel path transistor and the second input of the error amplifier, and coupling a control electrode of the current limit transistor to a second bias voltage.

20. A low drop out (LDO) voltage regulator with low quiescent current and at least a predetermined phase margin despite large variations in load current, comprising:

(a) a pass transistor and means for applying an input voltage to a first electrode of the pass transistor and means for coupling a second electrode of the pass transistor to apply an output voltage to a load;

(b) means for coupling a first input of an error amplifier to a reference voltage and means for coupling an output of the error amplifier to a control electrode of the pass transistor;

(c) means for coupling a feedback resistance between the output voltage and a second input of the error amplifier; and

(d) parallel path means coupled between the input voltage and the second input of the error amplifier for compensating a feedback loop of the LDO voltage regulator.