MULTIPLE CHANNEL BALLAST AND NETWORKABLE TOPOLOGY AND SYSTEM INCLUDING POWER LINE CARRIER APPLICATIONS

• US 20100052731A1
• Filed: 07/07/2009
• Published: 03/04/2010
• Est. Priority Date: 06/03/2002
• Status: Active Grant

• Current Assignee: S.t.l. Energy Solutions And Technologies Ltd.
• Original Assignee: Systel Development & Industries Ltd.
• Inventors: LEV, ARIE, KUHLIK, YURI, RABINOVITZ, EYTAN, RUBIN, DANIEL, NOGTEV, BORIS, MOGILNER, RAFAEL
• Granted Patent: US 8,036,321 B2
• Time in Patent Office: Days
• US Class Current: 327/27
• CPC Class Codes: H03M 1/129 Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling H03M1/18 takes precedence; Out-of-range indication
• CPC Class Codes: H05B 47/185 via power line carrier transmission

Abstract

Control systems and methods for independent control of power systems, particularly lighting network branches, and separate control of individual branch components. Multi-branch systems comprise independently controllable branches that inter-communicate via PLC communications. In each branch, components such as ballasts, local control units, sensors, actuators, and repeaters, may exchange commands and queries independently of a branch remote control unit (BRCU). Alternatively, a BRCU may manage or arbitrate communications, or interact with other BRCUs, other control units and external management systems. Ballasts include a multi-channel ballast that enables close-loop control of individual fixtures, or of individual dimmable or non-dimmable lamps within a fixture. The close-loop control is facilitated by sampling circuits/sensors co-located with each controlled fixture or lamp. All controllers are preferably implemented using an integrated digital controller. The PLC communication is preferably carried out by a direct spread spectrum method that eliminates side lobes from a cross-correlation function, using an anti-collision protocol.

Claims

1. A method of detecting an input signal, comprising the steps of:

a) sampling a plurality N of input signal samples;

b) detecting a coincidence between the N input signal samples and N corresponding samples of a reference signal; and

c) generating a 1-hit output value indicative of the coincidence.

2. The method of claim 1, wherein the step of detecting a coincidence includes detecting an absolute coincidence between all the N input signal samples and all the N corresponding reference signal samples.

3. The method of claim 2, wherein the step of generating a 1-bit output value includes generating a positive value indicative of the absolute coincidence.

4. The method of claim 3, wherein detecting an absolute coincidence includes:

i. providing the N input signal samples to N XOR logic gates,

ii. providing outputs of the N XOR logic gates to an OR logic gate, and

iii. generating from the OR logic gate the 1-bit output value.

5. The method of claim 1, further comprising the step of.

d) integrating the 1-bit output value to obtain an integrated result.

6. The method of claim 5, wherein integrating the 1-bit output value includes increasing an integration result by the 1-bit output value when the 1-hit output value is positive, and decreasing the integration result by the 1-bit output value when the 1-bit output value is negative.

7. The method of claim 6, further comprising the step of:

e) comparing the integration result with a threshold value.

8. The method of claim 1, wherein the input signal is a Direct Sequence Spread Spectrum (DSSS) modulated signal transmitted over a power line.

9. An apparatus for detecting an input signal, comprising:

a) a delay line configured to provide a plurality N of input signal samples; and

b) at least one symbol decoder configured to detect a coincidence between the N input signal samples and N corresponding samples of a reference signal, and to generate a 1-bit value indicative of the coincidence.

10. The apparatus of claim 9, wherein the symbol decoder is configured to detect the coincidence by providing the N input signal samples to N XOR logic gates, by providing outputs of the N XOR logic gates to an OR logic gate, and by generating from the OR logic gate the 1-bit output value.

11. The apparatus of claim 10, wherein the symbol decoder is further configured to integrate the 1-bit output value by increasing an integration result by the 1-bit output value when the 1-bit output value is positive, and by decreasing the integration result by the 1-bit output value when the 1-bit output value is negative.

12. The apparatus of claim 11, further comprising a symbol detector configured to compare the integration result with a symbol threshold.

13. The apparatus of claim 9, wherein the apparatus is configured to be coupled to a power line and wherein the input signal is a Direct Sequence Spread Spectrum modulated signal transmitted over the power line.