DELAY LOCKED LOOP CIRCUIT

• US 20100052748A1
• Filed: 12/30/2008
• Published: 03/04/2010
• Est. Priority Date: 09/02/2008
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: KIM, Tae-Kyun
• Granted Patent: US 7,843,240 B2
• Time in Patent Office: Days
• US Class Current: 327/158
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop

Abstract

A delay locked loop circuit includes a delay locking unit configured to output an internal clock by delaying a reference clock as much as a first delay amount in response to a phase comparison result of comparing a phase of the reference clock with a phase of a feedback clock that is generated based on delay modeling of a semiconductor memory device, and a noise sensor configured to control variation of the first delay amount caused by an external noise to be less than a second delay amount after locking the internal clock.

Claims

1. A delay locked loop circuit, comprising:

a delay locking unit configured to output an internal clock by delaying a reference clock as much as a first delay amount in response to a phase comparison result of comparing a phase of the reference clock with a phase of a feedback clock that is generated in response to delay modeling of a semiconductor memory device; and

a noise sensor configured to control variation of the first delay amount caused by an external noise to be less than a second delay amount after locking the internal clock.

2. The delay locked loop circuit of claim 1, wherein the reference clock is further delayed as much as the second delay amount than an external clock of the semiconductor memory device.

3. The delay locked loop circuit of claim 2, wherein the delay modeling of the semiconductor memory device includes delaying the internal clock signal by the second delay amount.

4. The delay locked loop circuit of claim 3, wherein the noise sensor includes:

a first phase comparator configured to generate a first phase comparison signal that is enabled when phases of the external clock and the feedback are inverted; and

a monitoring unit configured to disable variation of the first delay amount when the first phase comparison signal is enabled.

5. The delay locked loop circuit of claim 4, wherein the noise sensor further including a second phase comparator for generating a second phase comparison signal that is enabled when the reference clock is in advance by the second delay amount than compared to the feedback clock, and wherein the monitoring unit disables variation of the first delay amount when the second phase comparison signal is enabled.

6. The delay locked loop circuit of claim 4, wherein the noise sensor further including a cycle sensor for controlling the variation in response to a clock cycle in the delay locked loop circuit.

7. The delay locked loop circuit of claim 1, wherein the noise sensor is configured to secures a data margin of the semiconductor memory device as much as the second delay amount.

8. A delay locked loop circuit comprising:

a phase comparator configured to generate a first comparison signal by detecting a phase difference of a reference clock and a second feedback clock;

a delay controller configured to decide a first delay amount in response to the first phase comparison signal;

a first delay unit configured to output an internal clock by delaying the reference clock as much as the first delay amount;

a replica model unit configured to receive the internal clock and output a first feedback clock;

a second delay unit configured to output the reference clock by delaying an external clock of a semiconductor memory device as much as a second delay amount;

a third delay unit configured to output the second feedback clock by delaying the first feedback clock as much as the second delay amount; and

a noise controller configured to control variation of the first delay amount by sensing whether the first delay amount varies due to an external noise or not when the internal clock is locked.

9. The delay locked loop circuit of claim 8, wherein the delay locked loop circuit further including a cycle sensor for controlling the variation according to a cycle of the external clock.

10. The delay locked loop circuit of claim 9, wherein the noise controller includes:

a first phase comparator configured to generate a second phase comparison signal that is enabled when the external clock advances the second feedback clock in phase;

a second phase comparator configured to generate a third comparison signal that is enabled when the reference clock advances the first feedback clock in phase; and

a monitoring unit configured to disable the delay controller when the second phase comparison signal or the third comparison signal is enabled.

11. The delay locked loop circuit of claim 9, wherein the second delay amount increases as a cycle of the external clock extends.

12. The delay locked loop circuit of claim 9, wherein noise controller is configured to obtain a data margin of the semiconductor memory device as much as the second delay amount.