WIDEBAND OVERVOLTAGE PROTECTION CIRCUIT

• US 20100053831A1
• Filed: 09/02/2008
• Published: 03/04/2010
• Est. Priority Date: 09/02/2008
• Status: Abandoned Application

• Current Assignee: Consejo Superior de Investigaciones Científicas,
• Original Assignee: Consejo Superior de Investigaciones Científicas,
• Inventors: Fritsch Yusta, Carlos, Camacho Sosa-Dias, Jorge
• Application Number:
  US12/202,897
• Publication Number:
  US 20100053831A1
• Time in Patent Office: Days
• US Class Current: 361/91.500
• CPC Class Codes: H02H 3/22 of short duration, e.g. lightning

Abstract

The present patent application describes an approach to the protection of voltage sensitive instruments using a protection circuit that may be easily integrated in a three-terminal device, and which overcomes the drawbacks of previous approaches. The protection circuit of the invention performs very fast against overvoltages (in a few nanoseconds), automatically switching to a low impedance conduction state as soon as the overvoltage situation ends. It also minimizes insertion losses, shows a very low level of thermal noise and allows for obtaining broad bandwidths due to its low serial impedance in the conduction state. Furthermore, it does not require any power source or control signal.

Claims

1. Protection circuit (P), for protecting an instrument against overvoltages, comprising:

one MOSFET depletion transistor (Q1), having its gate (G1) connected to the input signal Vx and its drain (D1) connected to the output signal Vy;

a first resistor (R1), connected between source (S1) of the transistor (Q1) and input signal Vx;

a second resistor (R2), connected between source (S1) of the transistor (Q1) and ground (GND);

a third resistor (R3), connected between drain (D1) of the transistor (Q1) and ground (GND);

a first diode (DB), having its anode connected to the output signal Vy and its cathode connected to ground (GND);

a second diode (DA), having its cathode connected to the output signal Vy and its anode connected to ground (GND).

2. Protection circuit (P) according to claim 1, wherein the MOSFET depletion transistor (Q1) is an N-channel type transistor.

3. Protection circuit (P) according to claim 1, wherein the MOSFET depletion transistor (Q1) is an P-channel type transistor.

4. Protection circuit (P′

, P″

), for protecting an instrument against overvoltages, comprising;

a first MOSFET depletion transistor (Q1), having its drain (D1) connected to the input signal Vx;

a second MOSFET depletion transistor (Q2), having its drain (D2) connected to the output signal Vy;

a first diode (DB), having its anode connected to the output signal Vy and its cathode connected to ground (GND);

a second diode (DA), having its cathode connected to the output signal Vy and its anode connected to ground (GND).

wherein the gate (G1) of the first transistor (Q1) is connected to the source (S2) of the second transistor (Q2), the gate (G2) of the second transistor (Q2) is connected to the source (S1) of the first transistor (Q1) and the source (S1) of the first transistor (Q1) is connected to the source (S2) of the second transistor (Q2).

5. Protection circuit (P″

) according to claim 4, wherein the source (S1) of the first transistor (Q1) is connected to the source (S2) of the second transistor (Q2) through a resistor (R).

6. Protection circuit (P′

, P″

) according to claim 4, wherein both MOSFET depletion transistors (Q1, Q2) are N-channel type transistors.

7. Protection circuit (P′

, P″

) according to claim 4, wherein both MOSFET depletion transistors (Q1, Q2) are P-channel type transistors.

8. Protection circuit (P′

″

) for protecting a device against overvoltages, comprising;

a first MOSFET depletion transistor (Q1), having its gate (G1) connected to the input signal Vx;

a second MOSFET depletion transistor (Q2), having its gate (G2) and its source (S2) connected to the output signal Vy and its drain (D2) connected to the drain (D1) of the first transistor (Q1);

a first resistor (R1), connected between the source (S1) of the first transistor (Q1) and the input signal Vx;

a second resistor (R2), connected between the source (S1) of the first transistor (Q1) and ground (GND);

a third resistor (R3), connected between the drain (D1) of the first transistor (Q1) and ground (GND);

a first diode (DB), having its anode connected to the output signal Vy and its cathode connected to ground (GND);

a second diode (DA), having its cathode connected to the output signal Vy and its anode connected to ground (GND).

9. Protection circuit (P′

″

) according to claim 8, wherein the source (S2) of the second transistor (Q2) is connected to the output signal Vy through a resistor.

10. Protection circuit (P′

″

) according to claim 8, wherein both MOSFET depletion transistors (Q1, Q2) are N-channel type transistors.

11. Protection circuit (P′

″

) according to claim 8, wherein both MOSFET depletion transistors (Q1, Q2) are P-channel type transistors.

12. A voltage protection circuit, comprising:

a current regulator configured to receive an input voltage, the regulator comprising;

a switch;

a first diode having a first side connected to an output of the switch and a second side connected to electrical ground, the first diode having a predetermined conductive direction; and

a second diode connected in parallel with the first diode, the second diode having a conductive direction opposite to the conductive direction of the first diode,

wherein a protected output voltage is formed at the connection between the switch and the first diode.

13. The circuit of claim 12, wherein the switch comprises a MOSFET.

14. The circuit of claim 13, further comprising a resistive divider across the input voltage, wherein the input voltage is provided to the gate of the MOSFET and the divided voltage is provided to the source of the MOSFET.

15. The circuit of claim 13, further comprising a second MOSFET, wherein:

the drain of the first MOSFET is connected to the input voltage;

the source of the first MOSFET, the source of the second MOSFET, the gate of the first MOSFET and the gate of the second MOSFET are all electrically connected; and

the drain of the second MOSFET is connected to the first diode.

16. The circuit of claim 13, further comprising:

a second MOSFET; and

a predetermined resistor connected between the source of the first MOSFET and the source of the second MOSFET,

wherein;

the drain of the first MOSFET is connected to the input voltage;

the source of the first MOSFET is connected to the gate of the second MOSFET;

the source of the second MOSFET is connected to the gate of the first MOSFET; and

the drain of the second MOSFET is connected to the first diode.

17. The circuit of claim 13, comprising:

a second MOSFET, wherein the drain of the first MOSFET is connected to the drain of the second MOSFET, and the source of the second MOSFET is connected to the gate of the second MOSFET and connected to the first diode;

a predetermined resistor connected between the drain of the first MOSFET and electrical ground; and

a resistive divider across the input voltage, wherein the input voltage is provided to the gate of the first MOSFET and the divided voltage is provided to the source of the MOSFET,