Split Gate Non-Volatile Flash Memory Cell Having a Floating Gate, Control Gate, Select Gate and an Erase Gate with an Overhang Over the Floating Gate, Array and Method of Manufacturing

• US 20100054043A1
• Filed: 11/13/2009
• Published: 03/04/2010
• Est. Priority Date: 08/06/2007
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Hu, Yaw Wen, Liu, Xian, Tkachev, Yuri, Markov, Viktor, Levi, Amitay, Jia, James Yingbo, Kotov, Alexander, Su, Chien-Sheng
• Granted Patent: US 7,868,375 B2
• Time in Patent Office: Days
• US Class Current: 365/185.290
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

Claims

1. A non-volatile memory cell comprising:

a substrate of a substantially single crystalline material of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, spaced apart from the first region, forming a channel region therebetween;

a select gate insulated and spaced apart from a first portion of the channel region adjacent to the first region;

a floating gate insulated and spaced apart from a second portion of the channel region;

the floating gate having a first end closest to the select gate and a second end furthest away from the select gate;

said floating gate having a top surface and a bottom surface opposite thereto, with said bottom surface facing the channel region, said floating gate having a tip on the top surface and at the second end;

a tunneling barrier covering said tip, said barrier for permitting charges to pass therethrough during an erase operation;

a control gate having a top surface and a bottom surface opposite thereto, with said bottom surface insulated from and facing the top surface of the floating gate;

said control gate insulated and adjacent to the selected gate, said control gate having a first end closest to the select gate and a second end furthest away from the select gate;

wherein said second end of the control gate is closer to a vertical line aligned with the first end of the floating gate than the second end of the floating gate, whereby a portion of the top surface of the floating gate is not facing the bottom surface of the control gate;

an erase gate having a first portion insulated and spaced apart from the second region of the substrate and having a first end separated from the second end of the floating gate, and a second portion electrically connected to the first portion, said second portion above the floating gate and insulated therefrom and adjacent to the control gate, said second portion of the erase gate shielding said tunneling barrier from the control gate, said second portion of the erase gate separated from the floating gate by a first length measured in a direction substantially perpendicular to the direction from the first region to the second region;

said second portion having a second end closest to the second end of the control gate, said second portion of the erase gate having a second length measured from the second end of the second portion of the erase gate to a vertical line aligned with the first end of the first portion of the erase gate in a direction substantially parallel to the direction from the first region to the seconds region;

wherein said ratio of the second length to the first length is between approximately 1.0 and 2.5.

2. The cell of claim 1 wherein said two portions of the erase gate are monolithically formed.

3. The cell of claim 1 wherein said two portions of the erase gate are two separate portions electrically connected together.

4. The cell of claim 2 wherein said floating gate has a sharp corner, said corner being at the second end of the floating gate closest to the first portion of the erase gate.

5. The cell of claim 4 wherein the corner facilitates electron flow from the floating gate to the erase gate during the erase operation.

6. The cell of claim 2 wherein said floating gate is insulated and spaced apart from a portion of the second region.

7. The cell of claim 6 wherein the first portion of the channel region over which the select gate is insulated and spaced apart from abuts the first region.

8. The cell of claim 2 wherein said select gate is separated from the first end of the floating gate by a composite insulating material.

9. The cell of claim 8 wherein the composite insulating material is silicon dioxide and silicon nitride.

10. The cell of claim 2 wherein said select gate is separated from the first end of the floating gate by a homogeneous insulating material.

11. The cell of claim 10 wherein said homogeneous insulating material is silicon dioxide.

12. A process of fabricating an array of non-volatile memory cells comprising:

forming a plurality of first region and second region spaced apart therefrom of a second conductivity type in a substrate of a first conductivity type;

forming staked pairs of control gates and floating gates above the substrate on opposite sides of the first region, with each stacked pair having a control gate position above a floating gate, positioned above the substrate, with each of the floating gate and control gate having a length measured in a direction from the first region to the second region, and with the control gate having a length less than the length of the floating gate with each floating gate closest to the first region having an exposed portion not covered above by the control gate, and having a tip, with a tunneling barrier covering said tip;

forming an erase gate above the first region on the substrate between a stacked pair of control gate and floating gate, with said erase gate having two portions;

a first portion between the exposed portions of the floating gates and insulated therefrom, and having a first end closest to the floating gate; and

a second portion electrically connected to the first portion, said second portion above the exposed portion of the floating gate and insulated therefrom by said tunneling barrier, shielding the tunneling barrier from the control gate, wherein said second portion of the erase gate separated from the floating gate by a first length measured in a direction substantially perpendicular to the length direction;

said second portion having a first end closest to the control gate, said second portion of the erase gate having a second length measured from the first end of the second portion of the erase gate to a vertical line aligned with the first end of the first portion of the erase gate in a direction substantially parallel to the length direction;

wherein said ratio of the second length to the first length is between approximately 1.0 and 2.5;

forming select gates above the substrate and between the stacked pair of control gate and floating gate and the second region.

13. The process of claim 12 wherein said select gates and said erase gates are formed in the same step.

14. The process of claim 13 wherein said selected gates and said erase gates are formed by depositing a layer of silicon over, between and beside the stacked gates, and removing portions of the silicon above the stacked gates and above the second regions.

15. The process of claim 12 wherein said first region is formed after the stacked pairs of control gates and floating gates are formed.

16. The process of claim 15 wherein said second region is formed after the select gates and erase gates are formed.

17. The process of claim 16 wherein said first regions and second regions are formed by ion implantation.

18. A method of increasing the erase efficiency of a non-volatile memory cell of the type having a substrate of a substantially single crystalline material of a first conductivity type, with a first region of a second conductivity type, and a second region of the second conductivity type, spaced apart from the first region, forming a channel region therebetween;

said memory cell having a select gate insulated and spaced apart from a first portion of the channel region adjacent to the first region; and

having a floating gate insulated and spaced apart from a second portion of the channel region;

the floating gate having a first end closest to the select gate and a second end furthest away from the select gate;

said floating gate having a top surface and a bottom surface opposite thereto, with said bottom surface facing the channel region, and a tip on the top surface at the second end, with a tunneling barrier covering said tip;

said memory cell having a control gate with a top surface and a bottom surface opposite thereto, with said bottom surface insulated from and facing the top surface of the floating gate;

said control gate insulated and adjacent to the selected gate, said control gate having a first end closest to the select gate and a second end furthest away from the select gate;

wherein said second end of the control gate is closer to a vertical line aligned with the first end of the floating gate than the second end of the floating gate, whereby a portion of the top surface of the floating gate is not facing the bottom surface of the control gate;

said memory cell further having an erase gate having a first portion insulated and spaced apart from the second region of the substrate and having a first end separated from the second end of the floating gate, and a second portion electrically connected to the first portion and having a first end;

wherein said method comprising;

shielding the tunneling barrier from the control gate by positioning said second portion of the erase gate above the tip of the floating gate and insulated therefrom by said tunneling barrier with said first end adjacent to the control gate, said second portion of the erase gate separated from the floating gate by a first length measured in a direction substantially perpendicular to the direction from the first region to the second region;

with said first end of said second portion closest to the second end of the control gate, said second portion of the erase gate having a second length measured from the first end of the second portion of the erase gate to a vertical line aligned with the first end of the first portion of the erase gate in a direction substantially parallel to the direction from the first region to the seconds region; and

wherein said ratio of the second length to the first length is between approximately 1.0 and 2.5.

19. The method of claim 18 further comprising:

applying a negative voltage to the control gate, during an erase operation.