PROCESS OF PATTERNING SMALL SCALE DEVICES

• US 20100055577A1
• Filed: 08/29/2008
• Published: 03/04/2010
• Est. Priority Date: 08/29/2008
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Krivokapic, Zoran, Chen, An
• Granted Patent: US 7,939,247 B2
• Time in Patent Office: Days
• US Class Current: 430/5
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1606 Graphene

Abstract

A process is provided that includes forming a first mask on an underlying layer, where the mask has two adjacent portions with an open gap therebetween, and depositing a second mask material within the open gap and at an inclined angle with respect to an upper surface of the underlying layer to form a second mask. In another implementation, a process is provided that includes forming a first mask on an underlying layer, where the mask has a pattern that includes an open gap, and depositing a second mask material within the open gap to form a second mask, where particles of the second mask material are directed in parallel or substantially in parallel to a line at an inclined angle with respect to an upper surface of the underlying layer.

Claims

1. A process comprising:

forming a first mask on an underlying layer, the mask having two adjacent portions with an open gap therebetween; and

depositing a second mask material within the open gap and at an inclined angle with respect to an upper surface of the underlying layer to form a second mask.

2. The process according to claim 1, further comprising:

removing the first mask; and

performing processing on the underlying layer using the second mask as a mask for the processing.

3. The process according to claim 2, comprising performing processing on the underlying layer that includes etching of exposed portions of the underlying layer or performing ion implantation on exposed portions of the underlying layer.

4. The process according to claim 1, wherein the underlying layer is graphene.

5. The process according to claim 1, wherein the second mask has a feature size that is less than a feature size of the first mask.

6. The process according to claim 5, comprising forming the first mask on an underlying layer using a lithography process, wherein the feature size of the second mask is less than a resolution limit of the lithography process.

7. The process according to claim 6, wherein the underlying layer is graphene.

8. The process according to claim 7, further comprising:

removing the first mask; and

etching exposed portions of the underlying layer using the second mask as a mask.

9. The process according to claim 1, comprising depositing the second mask material by directing particles of the second mask material to travel in a straight line or in a substantially straight line from a source of the second mask material to the upper surface of the underlying layer.

10. The process according to claim 1, comprising controlling a feature size of the second mask by controlling an aspect ratio of the first mask and a value of the inclined angle.

11. A process comprising:

forming a first mask on an underlying layer, the mask having a pattern that includes an open gap; and

depositing a second mask material within the open gap to form a second mask, wherein particles of the second mask material are directed in parallel or substantially in parallel to a line at an inclined angle with respect to an upper surface of the underlying layer.

12. The process according to claim 11, further comprising:

removing the first mask; and

performing processing on the underlying layer using the second mask as a mask for the processing.

13. The process according to claim 12, comprising performing processing on the underlying layer that includes etching of exposed portions of the underlying layer or performing ion implantation on exposed portions of the underlying layer.

14. The process according to claim 11, wherein the underlying layer is graphene.

15. The process according to claim 11, wherein the second mask has a feature size that is less than a feature size of the first mask.

16. The process according to claim 15, comprising forming the first mask on an underlying layer using a lithography process, wherein the feature size of the second mask is less than a resolution limit of the lithography process.

17. The process according to claim 16, wherein the underlying layer is graphene.

18. The process according to claim 17, further comprising:

removing the first mask; and

etching exposed portions of the underlying layer using the second mask as a mask.

19. The process according to claim 11, comprising depositing the second mask material by directing the particles to travel in parallel or substantially in parallel to the line from a source of the second mask material to the upper surface of the underlying layer.

20. The process according to claim 11, comprising controlling a feature size of the second mask by controlling an aspect ratio of the first mask and a value of the inclined angle.