METHOD FOR FABRICATING AN INTEGRATED CIRCUIT

• US 20100055898A1
• Filed: 10/06/2008
• Published: 03/04/2010
• Est. Priority Date: 09/04/2008
• Status: Abandoned Application

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Nanya Technology Corporation
• Inventors: Kuo, Chi-Hsiang, Chang, Shuo-Che
• Application Number:
  US12/246,451
• Publication Number:
  US 20100055898A1
• Time in Patent Office: Days
• US Class Current: 438/653
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence

Abstract

A method for fabricating an integrated circuit is provided. A substrate having thereon a first conductive wire and a second conductive wire is provided. A liner is formed on the first conductive wire and second conductive wire. An ashable material layer is filled into a gap between the first conductive wire and second conductive wire. The ashable material layer is then polished to expose a portion of the liner. A cap layer is formed on the ashable material layer and on the exposed liner. A through hole is etched into the cap layer to expose a portion of the ashable material layer. Thereafter, the ashable material layer is removed by way of the through hole.

Claims

1. A method for fabricating an integrated circuit, comprising the steps of:

providing a substrate having thereon a first conductive wire and a second conductive wire;

forming a material layer on the substrate to cover the first conductive wire and the second conductive wire and fill into a space between the first conductive wire and the second conductive wire;

masking the material layer; and

removing the material layer.

2. The method of claim 1, wherein prior to the material layer formation step, a liner layer is formed on the substrate.

3. The method of claim 2, wherein the liner layer comprises SiO₂, Si₃N₄, SiON, SiC, SiOC or SiCN.

4. The method of claim 2, wherein the liner layer protects the first and the second conductive wires from corrosion and acts as a polishing stop layer.

5. The method of claim 1, wherein the material layer selectively comprises carbon layer and fluorine-doped carbon layer.

6. The method of claim 1, wherein the space is filled with the material layer.

7. The method of claim 1, wherein the material layer sustains at least 350°

C.

8. The method of claim 1, wherein the material layer is removed by using oxygen plasma.

9. The method of claim 1, further comprising the following step after the material layer removing step:

forming a dielectric layer over the substrate to form a hermetic air gap between the first conductive wire and the second conductive wire.

10. The method of claim 9, wherein the dielectric layer selectively comprises silicon oxide and low-k dielectric materials.

11. A method for fabricating an integrated circuit, comprising the steps of:

providing a substrate having thereon a first conductive wire and a second conductive wire;

forming a liner layer on the first conductive wire and the second conductive wire;

forming an ashable material layer on the liner layer and the ashable material layer filling into a space between the first conductive wire and the second conductive wire;

performing a planarization process to polish away a portion of the ashable material layer, thereby exposing a portion of the liner layer;

forming a cap layer on the ashable material layer and on the exposed liner layer;

forming a through hole in the cap layer to expose a portion of the ashable material layer; and

removing the ashable material layer by way of the through hole, thereby forming an air gap between the first conductive wire and the second conductive wire.

12. The method of claim 11, wherein the liner layer comprises SiO₂, Si₃N₄, SiON, SiC, SiOC or SiCN.

13. The method of claim 11, wherein the liner layer protects the first and the second conductive wires from corrosion and acts as a polishing stop layer.

14. The method of claim 11, wherein the ashable material layer comprises carbon layer or fluorine-doped carbon layer.

15. The method of claim 14, wherein the space is filled with the material layer.

16. The method of claim 11, wherein the cap layer selectively comprises silicon oxide, silicon nitride and low-k materials.

17. The method of claim 11, wherein the ashable material layer sustains at least 350°

C.

18. The method of claim 11, wherein the ashable material layer is removed by using oxygen plasma.

19. The method of claim 11 further comprising the following step after the ashable material layer removing step:

forming a dielectric layer over the substrate to seal the through hole.

20. The method of claim 19, wherein the dielectric layer selectively comprises silicon oxide or low-k dielectric materials.