Providing Code To A Programmable Device

• US 20100058311A1
• Filed: 06/09/2009
• Published: 03/04/2010
• Est. Priority Date: 09/02/2008
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Network Communications Incorporated (Fujitsu Limited)
• Inventors: McNeil, Roy C. JR., Terwilliger, David W.
• Granted Patent: US 9,495,250 B2
• Time in Patent Office: Days
• US Class Current: 717/168
• CPC Class Codes: G06F 11/1433 during software upgrading
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 12/16 Protection against loss of memory contents contains no material, see G06F11/00
• CPC Class Codes: G06F 9/44 Arrangements for executing specific programs
• CPC Class Codes: G06F 9/445 Program loading or initiating bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57
• CPC Class Codes: G06F 9/44536 Selecting among different versions
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Abstract

According to one embodiment, providing a bitstream to one or more programmable devices of a service unit card includes receiving the bitstream at a snooper of the service unit card. The snooper determines whether the bitstream is current. If the bitstream is current, the bitstream is loaded onto the programmable devices. If the bitstream is not current, the received bitstream is discarded, and a substitute bitstream is identified. The substitute bitstream is loaded onto the programmable devices.

Claims

1. A method comprising:

receiving, at a snooper of a service unit card, a bitstream, the bitstream for one or more programmable devices of the service unit card;

determining whether the bitstream is current;

if the bitstream is current, loading the bitstream onto the one or more programmable devices; and

if the bitstream is not current;

discarding the received bitstream;

identifying a substitute bitstream stored in a memory; and

loading the substitute bitstream onto the one or more programmable devices.

2. The method of claim 1, the substitute bitstream being pre-compiled.

3. The method of claim 1, the receiving, at the snooper of a service unit card, the bitstream further comprising:

receiving the bitstream from a master controller unit.

4. The method of claim 1, the determining whether the bitstream is current further comprising:

examining a cyclic redundancy check (CRC) block to determine whether the bitstream is current.

5. The method of claim 1, the determining whether the bitstream is current further comprising:

determining that the bitstream is not current if a device revision level of the one or more programmable devices is more current than a bitstream revision level of the bitstream.

6. An apparatus comprising:

one or more memories, each memory configured to store a substitute bitstream;

one or more programmable devices; and

a snooper configured to;

receive a bitstream for the one or more programmable devices;

determine whether the bitstream is current;

if the bitstream is current, load the bitstream onto the one or more programmable devices; and

if the bitstream is not current;

discard the received bitstream;

identify a substitute bitstream stored in a memory; and

load the substitute bitstream onto the one or more programmable devices.

7. The apparatus of claim 6, the substitute bitstream being pre-compiled.

8. The apparatus of claim 6, the snooper configured to receive the bitstream by:

receiving the bitstream from a master controller unit.

9. The apparatus of claim 6, the snooper configured to determine whether the bitstream is current by:

examining a cyclic redundancy check (CRC) block to determine whether the bitstream is current.

10. The apparatus of claim 6, the snooper configured to determine whether the bitstream is current by:

determining that the bitstream is not current if a device revision level of the one or more programmable devices is more current than a bitstream revision level of the bitstream.

11. The apparatus of claim 6, further comprising:

a master controller unit configured to provide the bitstream to the snooper.

12. A method comprising:

determining, by a loader of a service unit card, whether downloaded code is current, the downloaded code stored in a first memory of a plurality of memories of the service unit card;

if the downloaded code is current, instructing a processor to execute the downloaded code stored in the first memory; and

if the downloaded code is not current, instructing the processor to execute substitute code stored in one or more other memories of the plurality of memories.

13. The method of claim 12, the one or more memories comprising one or more flash memories.

14. The method of claim 12, further comprising:

entering, by the processor, an initialization state; and

loading, by the processor, the loader in response to entering the initialization state.

15. The method of claim 12, the one or more memories comprising a primary memory and a backup memory.

16. The method of claim 12, the instructing the processor to execute substitute code stored in one or more other memories of the plurality of memories further comprising:

instructing the processor to retrieve a field programmable gate array (FPGA) image from the first memory.

17. An apparatus comprising:

a plurality of memories comprising;

a first memory configured to store downloaded code; and

one or more other memories configured to store substitute code;

a processor configured to execute code; and

a loader configured to;

determine whether the downloaded code is current;

if the downloaded code is current, instruct the processor to execute the downloaded code; and

if the downloaded code is not current, instruct the processor to execute the substitute code.

18. The apparatus of claim 17, the one or more memories comprising one or more flash memories.

19. The apparatus of claim 17, the processor configured to:

enter an initialization state; and

load the loader in response to entering the initialization state.

20. The apparatus of claim 17, the one or more memories comprising a primary memory and a backup memory.

21. The apparatus of claim 17, the loader configured to instruct the processor to execute substitute code by:

instructing the processor to retrieve a field programmable gate array (FPGA) image from the first memory.

22. The apparatus of claim 17, further comprising:

a master controller unit configured to provide the downloaded code.