Stacking Integrated Circuits containing Serializer and Deserializer Blocks using Through Silicon Via

• US 20100058580A1
• Filed: 09/06/2008
• Published: 03/11/2010
• Est. Priority Date: 09/06/2008
• Status: Active Grant

• Current Assignee: Farhang Yazdani
• Original Assignee: Farhang Yazdani
• Inventors: Yazdani, Farhang
• Granted Patent: US 8,014,166 B2
• Time in Patent Office: Days
• US Class Current: 29/740
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: Y10T 29/53174 : Means to fasten electrical component to wiring board, base, or substrate
• CPC Class Codes: Y10T 29/53178 : Chip component
• CPC Class Codes: Y10T 29/53183 : Multilead component

Abstract

Methods and systems for stacking multiple chips with high speed serialiser/deserialiser blocks are presented. These methods make use of Through Silicon Via (TSV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serialiser/deserialiser blocks, using the TSVs.

Claims

1. A system for stacking Integrated Circuits vertically to create a three dimensional chip package, said system comprising:

one or more silicon die;

one or more redistribution layers;

one or more through silicon via;

one or more contact pads;

a dielectric substrate;

high speed serial circuits;

wherein said one or more silicon die contain said high speed serial circuits;

wherein said high speed serial circuits are staggered on said one or more silicon die;

wherein said one or more silicon die are stacked vertically on top of each other in such a way that said high speed serial circuits of said one or more stacked silicon die do not block each other;

wherein one or more fiducials are used to optically align said one or more silicon die that are stacked vertically on top of each other;

wherein said one or more through silicon via are placed in said high speed serial circuits;

wherein said one or more distribution layer is placed between two of said one or more silicon die;

wherein said one or more silicon die along with said one or more redistribution layer are stacked on top of said dielectric substrate;

wherein said one or more contact pads are placed on said dielectric substrate;

wherein said one or more distribution layers are used to interconnect said one or more through silicon via belonging to said two of said one or more silicon die or to interconnect said one or more through silicon via to said one or more contact pads.

2. A system as stated in claim 1, wherein said fiducials are one of cross, square, circle, or equal symbols.

3. A system as stated in claim 1, wherein said high speed serial circuits are placed at one or more peripheries of said one or more silicon die and wherein said one or more silicon die are stacked vertically on top of each other by rotating said one or more silicon die in multiples of ninety degrees in such a way that said high speed serial circuits placed at said one or more peripheries of said one or more stacked silicon die do not block each other.

4. A system as stated in claim 1, wherein said one or more silicon die and said one or more redistribution layer contain said one or more through silicon via, blind via, buried via, or any combination of vias.

5. A system as stated in claim 1, wherein one or more contact pads are created on said one or more redistribution layer to create a contact point for the said one or more through silicon vias.

6. A system as stated in claim 1, wherein tear drop connections are used for connecting traces on said one or more redistribution layer to said one or more through silicon via.

7. A system as stated in claim 1, wherein said one or more silicon die contain digital circuits.

8. A system as stated in claim 1, wherein said one or more silicon die use said one or more through silicon vias for said high speed serial circuits and wirebond for said digital circuits.

9. A system as stated in claim 1, wherein said chip package uses flip-chip technology.

10. A system as stated in claim 1, wherein one or more of said high speed serial circuits are Serial Gigabit Media Independent Interface.

11. A system as stated in claim 1, wherein said high speed serial circuits operate in full-duplex mode.

12. A system as stated in claim 1, wherein said high speed serial circuits operates at radio frequencies.

13. A system as stated in claim 1, wherein said one or more through silicon via are scattered in the middle of said one or more silicon die, and one or more test pads are placed at the extreme periphery of said one or more silicon dies.

14. A system as stated in claim 1, wherein said one or more redistribution layer contains plans.

15. A system as stated in claim 1, wherein said three dimensional chip is used in Gigabit Ethernet systems.

16. A system as stated in claim 1, wherein said three dimensional chip is used in wireless network routers.

17. A system as stated in claim 1, wherein said three dimensional chip is used in fiber optic communications or storage systems.

18. A system as stated in claim 1, wherein said three dimensional chip is used in cellular phones.

19. A system as stated in claim 1, wherein said one or more contact pads are circular.

20. A system as stated in claim 1, wherein said one or more redistribution layer is covered with solder resist or adhesive.