Shared masks for x-lines and shared masks for y-lines for fabrication of 3D memory arrays

• US 20100059796A1
• Filed: 09/09/2008
• Published: 03/11/2010
• Est. Priority Date: 09/09/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E.
• Granted Patent: US 7,943,515 B2
• Time in Patent Office: Days
• US Class Current: 257/208
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/10 including a plurality of individual components in a repetitive configuration

Abstract

A structure and a method of manufacturing a three dimensional memory using a number of bit line masks that is less than the number of device layers. A first bit line mask is used to form a first bit line layer in a first device level. The first bit line layer comprises first bit lines. The first bit line mask is also used to form a second bit line layer in a second device level. The second bit line layer comprises second bit lines. The first bit lines and the second bit lines have different electrical connections to a bit line connection level despite employing the same mask pattern.

Claims

1. A method of manufacturing a three dimensional semiconductor device comprising:

using a first bit line mask to form a first bit line layer in a first device level, wherein the first bit line layer comprises first bit lines; and

using the first bit line mask to form a second bit line layer in a second device level, wherein the second bit line layer comprises second bit lines,

wherein the first bit lines and the second bit lines have different electrical connections to a bit line connection level.

2. The method of claim 1 further comprising:

using a first device mask set to form a first device layer in the first device level, wherein the first device layer comprises first devices, wherein the first devices are electrically connected to the first bit lines; and

using the first device mask set to form a second device layer in the second device level, wherein the second device layer comprises second devices, wherein the second devices are electrically connected to the second bit lines,

wherein the first device mask set comprises at least one device mask.

3. The method of claim 2 wherein the first devices and second devices comprise a one time programmable or a rewritable cell selected from at least one of antifuse, fuse, diode and antifuse arranged in a series, polysilicon memory effect cell, metal oxide memory, switchable complex metal oxide, carbon nanotube memory, phase change material memory, conductive bridge element, switchable polymer memory, or thin deposited carbon switchable resistor.

4. The method of claim 3 further comprising:

using a first word line mask to form a first word line layer, wherein the first word line layer comprises first word lines, and wherein the first word lines are shared by the first device level and second device level.

5. The method of claim 3 further comprising:

using a first word line mask to form a first word line layer in the first device level, wherein the first word line layer comprises first word lines, wherein the first devices are electrically connected to the first word lines; and

using the first word line mask to form a second word line layer in the second device level, wherein the second word line layer comprises second word lines, wherein the second devices are electrically connected to the second word lines,

wherein the first word lines are electrically connected to the second word lines.

6. The method of claim 4 further comprising:

using at least two bit line masks to form bit line layers in a plurality of device levels, wherein the bit line layers comprise bit lines, wherein the bit lines of the respective device levels have different electrical connections to the bit line connection level.

7. The method of claim 6 further comprising:

using a first via mask to form via layers amongst the plurality of device levels, wherein the via layers comprise vias, wherein the vias are part of the different electrical connections to the bit line connection level.

8. The method of claim 7 comprising:

using the first bit line mask to form bit lines on three different device levels;

using a second bit line mask to form bit lines on two different device levels;

using a third bit line mask to form bit lines on two different device levels;

using a fourth bit line mask to form bit lines on one device level;

using the first word line mask to form word lines on four different word line layers;

using the first device mask set to form devices on eight different device levels;

using the first via mask to form four different via layers,

wherein the respective bit lines of the eight device levels have different electrical connections to the bit line connection level.

9. The method of claim 7 further comprising:

using a first strap mask to form electrical straps, wherein the electrical straps are part of the different electrical connections to the bit line connection level.

10. The method of claim 9 comprising:

using the first bit line mask to form bit lines on three different device levels;

using a second bit line mask to form bit lines on three different device levels;

using a third bit line mask to form bit lines on two different device levels;

using the first word line mask to form word lines on four different word line layers;

using the first device mask set to form devices on eight different device levels;

using the first via mask to form four different via layers;

using the first strap mask to form electrical straps,

wherein the respective bit lines of the eight device levels have different electrical connections to the bit line connection level.

11. The method of claim 9 comprising:

using the first bit line mask to form bit lines on three different device levels;

using a second bit line mask to form bit lines on two different device levels;

using a third bit line mask to form bit lines on two different device levels;

using a fourth bit line mask to form bit lines on one device level;

using the first word line mask to form word lines on four different word line layers;

using the first device mask set to form devices on eight different device levels;

using the first via mask to form four different via layers;

using the first strap mask to form electrical straps,

wherein the respective bit lines of the eight device levels have different electrical connections to the bit line connection level.

12. A three dimensional semiconductor device comprising:

a first bit line layer in a first device level, wherein the first bit line layer has a first bit line pattern, wherein the first bit line layer comprises first bit lines; and

a second bit line layer in a second device level, wherein the second bit line layer has the first bit line pattern, wherein the second bit line layer comprises second bit lines,

wherein the first bit lines and the second bit lines have different electrical connections to a bit line connection level.

13. The three dimensional semiconductor device of claim 12 further comprising:

a first device layer in the first device level, wherein the first device layer has a first device pattern, wherein the first device layer comprises first devices, wherein the first devices are electrically connected to the first bit lines; and

a second device layer in the second device level, wherein the second device layer has the first device pattern, wherein the second device layer comprises second devices, wherein the second devices are electrically connected to the second bit lines,

wherein the first device pattern is created using at least one device mask.

14. The three dimensional semiconductor device of claim 13 wherein the first devices and second devices comprise a one time programmable or a rewritable cell selected from at least one of antifuse, fuse, diode and antifuse arranged in a series, polysilicon memory effect cell, metal oxide memory, switchable complex metal oxide, carbon nanotube memory, phase change material memory, conductive bridge element, switchable polymer memory, or thin deposited carbon switchable resistor.

15. The three dimensional semiconductor device of claim 14 further comprising:

a first word line layer, wherein the first word line layer has a first word line pattern, wherein the first word line layer comprises first word lines, and wherein the first word lines are shared by the first device level and second device level.

16. The three dimensional semiconductor device of claim 14 further comprising:

a first word line layer in the first device level, wherein the first word line layer has a first word line pattern, wherein the first word line layer comprises first word lines, wherein the first devices are electrically connected to the first word lines; and

a second word line layer in the second device level, wherein the second word line layer has the first word line pattern, wherein the second word line layer comprises second word lines, wherein the second devices are electrically connected to the second word lines,

wherein the first word lines are electrically connected to the second word lines.

17. The three dimensional semiconductor device of claim 15 further comprising:

bit line layers in a plurality of device levels, wherein at least two of the bit line layers share a bit line pattern, wherein the bit line layers comprise bit lines, wherein the bit lines of the respective device levels have different electrical connections to the bit line connection level.

18. The three dimensional semiconductor device of claim 17 further comprising:

via layers amongst the plurality of device levels, wherein the via layers have a first via pattern, wherein the via layers comprise vias, wherein the vias are part of the different electrical connections to the bit line connection level.

19. The three dimensional semiconductor device of claim 18 wherein the device comprises eight device levels comprising:

a first three bit line layers on three different device levels, wherein the first three bit line layers share a first bit line pattern;

a first two bit line layers on two different device levels, wherein the first two bit line layers share a second bit line pattern;

a second two bit line layers on two different device levels, wherein the second two bit line layers share a third bit line pattern;

an eighth bit line layer, wherein the eighth bit line layer has a fourth bit line pattern;

four word line layers, wherein the four word line layers share a word line pattern;

eight device layers, wherein the eight device levels share a device layer pattern; and

four via layers, wherein the four via layers share a via layer pattern;

wherein the respective bit lines of the eight device levels have different electrical connections to the bit line connection level.

20. The three dimensional semiconductor device of claim 18 further comprising:

electrical straps, wherein the electrical straps are part of the different electrical connections to the bit line connection level.

21. The three dimensional semiconductor device of claim 20 wherein the device comprises eight device levels comprising:

a first three bit line layers on three different device levels, wherein the first three bit line layers share a first bit line pattern;

a second three bit line layers on three different device levels, wherein the second three bit line layers share a second bit line pattern;

a first two bit line layers on two different device levels, wherein the first two bit line layers share a third bit line pattern;

four word line layers, wherein the four word line layers share a word line pattern;

eight device layers, wherein the eight device levels share a device layer pattern;

four via layers, wherein the four via layers share a via layer pattern; and

an electrical strap layer, wherein the electrical strap layer includes electrical straps, wherein the electrical straps are part of at least some of the electrical connections to the bit line connection level,

wherein the respective bit lines of the eight device levels have different electrical connections to the bit line connection level.

22. The three dimensional semiconductor device of claim 20 wherein the device comprises eight device levels comprising:

a first three bit line layers on three different device levels, wherein the first three bit line layers share a first bit line pattern;

a first two bit line layers on two different device levels, wherein the first two bit line layers share a second bit line pattern;

a second two bit line layers on two different device levels, wherein the second two bit line layers share a third bit line pattern;

an eighth bit line level, wherein the eighth bit line level has a fourth bit line pattern;

four word line layers, wherein the four word line layers share a word line pattern;

eight device layers, wherein the eight device levels share a device layer pattern;

four via layers, wherein the four via layers share a via layer pattern; and

an electrical strap layer, wherein the electrical strap layer includes electrical straps, wherein the electrical straps are part of at least some of the electrical connections to the bit line connection level,

wherein the respective bit lines of the eight device levels have different electrical connections to the bit line connection level.