SEMICONDUCTOR DEVICE HAVING VERTICAL CHARGE-COMPENSATED STRUCTURE AND SUB-SURFACE CONNECTING LAYER AND METHOD

• US 20100059814A1
• Filed: 09/08/2008
• Published: 03/11/2010
• Est. Priority Date: 09/08/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Loechelt, Gary H., Zdebel, Peter J.
• Granted Patent: US 7,960,781 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one embodiment, a semiconductor device is formed having vertical localized charge-compensated trenches, trench control regions, and sub-surface doped layers. The vertical localized charge-compensated trenches include at least a pair of opposite conductivity type semiconductor layers. The trench control regions are configured to provide a generally vertical channel region electrically coupling source regions to the sub-surface doped layers. The sub-surface doped layers are further configured to electrically connect the drain-end of the channel to the vertical localized charge compensation trenches. Body regions are configured to isolate the sub-surface doped layers from the surface of the device.

Claims

1. A semiconductor device comprising:

a body of semiconductor material formed with a vertical charge compensation structure, wherein the vertical charge compensation structure includes at least one conduction layer of a first conductivity type semiconductor material and at least one compensation layer of a second conductivity type semiconductor material, wherein the second conductivity type is opposite to the first conductivity type;

a body region of the second conductivity type formed in the body of semiconductor material adjacent to the vertical charge compensation structure;

a source region of the first conductivity type formed adjacent the body region;

a trench control structure formed adjacent the source and body regions, wherein the source region is interposed between the trench control structure and the vertical charge compensation structure, wherein the trench control structure is configured to form a channel region within the body region; and

a doped region of the first conductivity type formed below the body region and configured to electrically connect a drain end of the channel region to the conduction layer.

2. The device of claim 1 further comprising a conductive layer overlying the major surface and electrically coupled to the source region, the body region and the compensation layer.

3. The device of claim 1, wherein a portion of the body of semiconductor material comprises the second conductivity type.

4. The device of claim 1, wherein the body of semiconductor material comprises the first conductivity type.

5. The device of claim 1, wherein the vertical charge compensation structure comprises a generally vertical trench having sidewalls and a lower surface, and wherein the conduction layer overlies the sidewalls and the lower surface, and wherein the compensation layer overlies the conduction layer.

6. The device of claim 1, wherein the body region electrically isolates the doped region from the major surface.

7. The device of claim 1 further comprising a body contact region of the second conductivity type formed in the body region, wherein the body contact region overlies an upper portion of the vertical charge compensation structure.

8. A semiconductor device comprising:

a semiconductor region having a major surface;

a vertical charge compensation structure formed in the semiconductor region extending from the major surface, wherein the vertical charge compensation structure includes a first semiconductor layer of a first conductivity adjoining the semiconductor region, and a second semiconductor layer of a second conductivity type opposite to the first conductivity type adjoining the first semiconductor layer, and wherein the first semiconductor layer is a conduction layer and wherein the second semiconductor layer is a compensation layer;

a trench control structure formed in the semiconductor region laterally spaced apart from the vertical charge compensation structure;

a body region adjoining and between the trench control and the vertical charge compensation structures, wherein the body region has the second conductivity type;

a source region overlying a portion of the body region and adjoining the trench control structure;

a doped region of the first conductivity underlying the body region and configured to provide a sub-surface current path between the source region and the conduction layer; and

a conductive layer overlying the major surface and electrically coupled to the source region, the body region and the compensation layer.

9. The device of claim 8 further comprising a buffer layer formed overlying the second semiconductor layer.

10. The device of claim 8 further comprising a buffer layer formed interposed between the first and second semiconductor layers.

11. The device of claim 8, wherein the conductive layer contacts vertical and horizontal surfaces of the source region.

12. The device of claim 8 further comprising a body contact region of the second conductivity type formed in portions of the body region.

13. The device of claim 12, wherein the body contact region overlies the vertical charge compensation structure.

14. The device of claim 8, wherein the semiconductor region comprises a semiconductor substrate of the first conductivity type and a semiconductor layer of the second conductivity type overlying the semiconductor substrate.

15. The device of claim 8, wherein the semiconductor region comprises a semiconductor substrate of the first conductivity and a semiconductor layer of the first conductivity type overlying the semiconductor substrate, and wherein the doped region has a higher dopant concentration than the semiconductor layer.

16. A method for forming a semiconductor device comprising the steps of:

providing a body of semiconductor material having a major surface;

forming a vertical charge compensated structure in the body of semiconductor material extending from the major surface, wherein the vertical charge compensated structure includes at least one conduction layer of a first conductivity type and at least one compensation layer of a second conductivity type opposite the first conductivity type;

forming a trench control structure in the body of semiconductor material;

forming a doped region of the first conductivity type in the body of semiconductor material;

forming a body region of the second conductivity type in the body of semiconductor material above the doped region; and

forming a source region of the first conductivity type formed adjacent the body region, wherein the source region is interposed between the trench control structure and the vertical charge compensated structure, and wherein the trench control structure is configured to form a channel region within the body region, and wherein the doped region is configured to electrically connect a drain end of the channel region to the conduction layer.

17. The method of claim 16 further comprising the step of forming a conductive layer overlying the major surface and electrically coupled to the source region, the body region and the compensation layer.

18. The method of claim 16, wherein the step of providing the body of semiconductor material includes providing a body of semiconductor material wherein the vertical charge compensated structure comprises a generally vertical trench having sidewalls and a lower surface, and wherein the conduction layer overlies the sidewalls and the lower surface, and wherein the compensation layer overlies the conduction layer.

19. The method of claim 16 further comprising the step of forming a body contact region of the second conductivity type in the body region, wherein the body contact region overlies an upper portion of the vertical charge compensated structure.

20. The method of claim 16, wherein the step of forming the trench control structure occurs after the step of forming the vertical charge compensated structure.

21. The method of claim 16, wherein the step of forming the trench control structure occurs before the step of forming the vertical charge compensated structure.