TRENCH GATE TYPE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

• US 20100059816A1
• Filed: 09/26/2008
• Published: 03/11/2010
• Est. Priority Date: 09/28/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Tabe, Tomonori, Shimada, Satoru, Yamaoka, Yoshikazu, Fujita, Kazunori
• Granted Patent: US 8,242,557 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The invention provides a trench gate type transistor in which the gate capacitance is reduced, the crystal defect is prevented and the gate breakdown voltage is enhanced. Trenches are formed in an N− type semiconductor layer. A uniformly thick silicon oxide film is formed on the bottom of each of the trenches and near the bottom, being round at corner portions. A silicon oxide film is formed on the upper portion of the sidewall of each of the trenches, which is thinner than the silicon oxide film and round at corner portions. Gate electrodes are formed from inside the trenches onto the outside thereof. The thick silicon oxide film reduces the gate capacitance, and the thin silicon oxide film on the upper portion provides good transistor characteristics. Furthermore, with the round corner portions, the crystal defect does not easily occur, and the gate electric field is dispersed to enhance the gate breakdown voltage.

Claims

1. A trench gate type transistor comprising:

a semiconductor layer having a trench formed therein;

a gate insulation film disposed in the trench and extending outside the trench so as to overlie a top surface of the semiconductor layer;

a gate electrode disposed on the gate insulation film; and

a body layer formed in the semiconductor layer so as to be in contact with the gate insulation film on a sidewall of the trench,

wherein, on the sidewall of the trench where the body layer is in contact with the gate insulation film, the gate insulation film comprises a first portion having a first thickness on an upper portion of the sidewall of the trench and a second portion having a second thickness on a lower portion of the sidewall of the trench, the second thickness being larger than the first thickness, and

the gate insulation film further comprises a third portion having the second thickness at a bottom of the trench.

2. The trench gate type transistor of claim 1, wherein the body layer is in contact with at least a portion of the first portion of the gate insulation film having the first thickness.

3. The trench gate type transistor of claim 1, wherein the gate insulation film is round at a top edge portion of the trench where the sidewall of the trench and the top surface of the semiconductor layer meet so as not to have an apex portion in a cross section thereof.

4. The trench gate type transistor of claim 1, further comprising a high breakdown voltage MOS transistor formed on the semiconductor layer comprising another gate insulation film made of the gate insulation film.

9. The trench gate type transistor of claim 1, wherein a bottom edge of the trench where the sidewall and the bottom of trench meet has a rounded shape.

5. A method of manufacturing a trench gate type transistor, comprising:

forming a trench in a semiconductor layer;

forming an oxide film on a front surface of the semiconductor layer and in the trench by thermally oxidizing the semiconductor layer;

forming a photoresist reinforcement film on the oxide film;

forming a photoresist layer on the photoresist reinforcement film;

leaving the photoresist layer and the photoresist reinforcement film in the trench by etching back the photoresist layer and the photoresist reinforcement film to expose the oxide film on the front surface of the semiconductor layer;

removing the oxide film from the front surface of the semiconductor layer and an upper portion of a sidewall of the trench by etching the exposed oxide film using the photoresist layer and the photoresist reinforcement film as a mask so that the oxide film remains at a bottom portion of the trench and a lower portion of the sidewall;

removing the photoresist layer and the photoresist reinforcement film;

forming another oxide film connected to the remaining oxide film, thinner than the remaining oxide film and disposed at the upper portion of the sidewall of the trench by thermal oxidation;

forming a gate electrode on the oxide film and the another oxide film; and

forming a body layer in the semiconductor layer along the trench so as to be in contact with at least the another oxide film.

7. The method of claim 5, wherein the photoresist reinforcement film comprises a silicon nitride film.

8. The method of claim 5, wherein the formation of the oxide film comprises thermally oxidizing the semiconductor layer so as to be round at a top edge portion of the trench so as not to have an apex portion in a cross section thereof.

6. A method of manufacturing a trench gate type transistor, comprising:

forming a trench in a semiconductor layer;

forming an oxide film on a front surface of the semiconductor layer and in the trench by thermally oxidizing the semiconductor layer;

forming a photoresist reinforcement film on the oxide film;

forming a BARC on the photoresist reinforcement film;

forming a photoresist layer on the BARC;

exposing the BARC in an active region by forming an opening in the photoresist layer so as to cover a peripheral region;

leaving the BARC and the photoresist reinforcement film in the trench by etching back the BARC and the photoresist reinforcement film using the photoresist layer as a mask to expose the oxide film in the active region and not to expose the oxide film in the peripheral region;

removing the oxide film from the front surface of the semiconductor layer and an upper portion of a sidewall of the trench by etching the exposed oxide film using the photoresist layer and the photoresist reinforcement film as a mask so that the oxide film remains at a bottom portion of the trench and a lower portion of the sidewall;

removing the photoresist layer, the BARC and the photoresist reinforcement film;

forming another oxide film connected to the remaining oxide film, thinner than the remaining oxide film and disposed at the upper portion of the sidewall of the trench by thermal oxidation;

forming a gate electrode on the oxide film and the another oxide film; and

forming a body layer in the semiconductor layer along the trench so as to be in contact with at least the another oxide film.

10. The method of claim 6, wherein the photoresist reinforcement film comprises a silicon nitride film.

11. The method of claim 6, wherein the formation of the oxide film comprises thermally oxidizing the semiconductor layer so as to be round at a top edge portion of the trench so as not to have an apex portion in a cross section thereof.